ASIC設計工程師如何保住飯碗？

mister_liu

Junior Physical Design Engineer

& Z& K! [* O3 h, m. y" E4 P! f公      司： famous IC company
工作地点：北京

" `* i) q' h' yPosition Tasks, Duties and Responsibilities
The ASIC Physical Design Engineer will:
4 s: \! F5 X6 x+ D2 @2 c/ g        Complete third party IP integration and ensure vendor guidelines are followed.
        Responsible for physical verification (DRC/LVS).
        IO ring design, fullchip floorplan.
1 |, A; }7 ^( D% i* _        Block level implementation.
        Work with front-end engineers to resolve problems and achieve design closure.
( n& M1 j7 d, Q
Candidate Qualifications:
) @6 x5 G/ m' ]Candidate must:
        Hold BSEE (MS preferred).
        Have minimum of 3 years hands-on experience in full flow IC back-end physical design and verification
        Be able to complete block and chip level tapeout quality LVS and  LVS and DRC.
1 O+ ]3 R7 W. c2 J% Z        Have the ability to independently identify and resolve design, tool, and flow problems.
( V6 W( ]- l# V- Z7 Q        Have related timing and physical concept.
) V; {+ m( d) ~        Be able to design and implement physical design strategies and methodologies for deep submicron designs.
. L. Q* \! s+ u" ]        Familiar with EDA tools.
        Familiar with Linux environments.  
% {* X$ Q$ Q* H( _! q
# h* ]9 _" @! z% k8 O4 Z- ZAny of the following is beneficial:
3 m$ V8 }" E$ v! S6 P6 z. j* B        STA constraint design
       Equivalence checking ?RTL to gates, and gates to gates.

ranica

Junior Physical Design Engineer

公      司：A famous IC company
工作地点：北京
' p5 V0 h6 u$ `( \) |
Position Tasks, Duties and Responsibilities
The ASIC Physical Design Engineer will:
* p5 z! Q: k1 Z        Complete third party IP integration and ensure vendor guidelines are followed.
        Responsible for physical verification (DRC/LVS).
/ x% u2 Y7 T8 i0 R        IO ring design, fullchip floorplan.
        Block level implementation.
        Work with front-end engineers to resolve problems and achieve design closure.

$ x- k) u  F) A$ g3 pCandidate Qualifications:
6 P+ k$ p$ Z) M! [Candidate must:
+ _8 V' l, c4 |        Hold BSEE (MS preferred).
5 f$ M. f5 k# n' N5 E! X        Have minimum of 3 years hands-on experience in full flow IC back-end physical design and verification
        Be able to complete block and chip level tapeout quality LVS and  LVS and DRC.
. \  x) V8 z% |! h3 ^: Z        Have the ability to independently identify and resolve design, tool, and flow problems.
        Have related timing and physical concept.
        Be able to design and implement physical design strategies and methodologies for deep submicron designs.
6 g: P: T1 v' T: U$ ?  T        Familiar with EDA tools.
        Familiar with Linux environments.  
7 _2 S0 _0 a9 ]2 e- d# E' }
3 k. n' v) f8 f6 Q* V3 ?) CAny of the following is beneficial:
1 q) u/ h2 `! B+ C        STA constraint design
       Equivalence checking ?RTL to gates, and gates to gates.

ranica

Sr. ASIC Design Engineer (encoder/decoder)

公      司：a leading developer of advanced digital imaging solution
. u% }  d* |/ h; X8 |! L工作地点：上海
( `2 o' d. A3 J
2 s5 @( c4 g: h& _" WPosition Overview: The candidate will join a team of  highly competent ASIC designers involved in design, verification, and implementation (ASIC) of advanced platform for XX''s future generation multi-media products.   

主要职责 (70%)
/ ^) W: E1 Q2 Z( E+ RIn-depth knowledge of TV encoder and decoder design. Good understanding of TV system design.  
0 p+ t; T) _7 x9 b  RProficiency on digital filter algorithms and hardware implementation.
) j4 S. O) Q; Y& d2 I+ Q) q- pDevelopment and verification of complex IP module, integration of the IP module into the Soc devices, top-level design handling, system level testing.
* R& y: y, W! a. S, |  G4 U# z0 C5 WParticipate in the FPGA platform development and lab debugging   

. R& Q5 O' p5 i' b7 S其他职责 (30%)
) S4 k. m9 m8 z+ ]Participate in block level architecture design Assisting embedded FW development.
职位要求
" F6 q& y- e/ y9 Q岗位资格
经验/技能
  _- ]. g( z" x; {1. Strong knowledge of TV technologies, knowledge of image signal process and CCTV system is a plus
% A* ^4 m" [5 Y2. Strong knowledge of ASIC design flow. Can define Micro-architecture of the IP module and /or sub-blocks. And able to write detailed engineering specifications.
3 }+ V. [% V+ P) T! X$ ~$ I3. Good communication skills, especially in technical writing and reporting;
4. Self-motivated and ability to excel in a team environment.   

教育
' ^7 L0 [/ J+ b8 E/ ^+ wMSEE/CE with 3+ years of industry experience

amatom

Senior Digital Design Engineer
) e" g" c( |* ^" f1 X  a' X
公      司：A leading semiconductor company
工作地点：香港
5 G: K8 x5 F4 j1 `+ X
Job Responsibilities:
* B, J, j2 c. P. m5 ~    Perform logic design, RTL coding, design verification, logic synthesis, DFT and static timing analysis
    Develop verification environment and coverage closure
/ b# I2 U1 i3 B. a! L0 X    Support wafer level testing and silicon evaluation
- T- X1 v- @7 Q0 g% @3 ~( c    Prepare technical documents
5 m7 \- X$ H+ Z$ y$ _
Job Requirements:
    B.Sc or above in Electronic Engineering or equivalent. Applicants with postgraduate degree would be considered as an advantage
) }/ J- ^7 k' q. T    5 Years or above of solid experience in one or more of the following areas: Verilog-based logic design and synthesis, constrained random    testbench with System Verilog & UVM, assertion based design verification or circuit-level SPICE simulations
    Knowledge of SoC and embedded system.
. c' }" C) {) L1 j  `  w+ ]4 W    Knowledge of scripting languages such as Perl, TCL and Make
. U6 H3 `- _6 ^3 H    Candidate with less experience will be considered as Digital Design Engineer

innoing123

Junior Physical Design Engineer
! C) L0 Y+ d2 e1 D! ]$ p8 V( X公      司：A famous IC company
工作地点：北京

6 c( s( Q% u! N: \Position Tasks, Duties and Responsibilities
# G$ x" s2 J6 s) n" [% b, yThe ASIC Physical Design Engineer will:
        Complete third party IP integration and ensure vendor guidelines are followed.
        Responsible for physical verification (DRC/LVS).
9 N+ }2 F. o% H! `  a6 A        IO ring design, fullchip floorplan.
        Block level implementation.
        Work with front-end engineers to resolve problems and achieve design closure.
. r2 ]$ k6 V$ Y" U
5 x4 g  c  H: z* B" JCandidate Qualifications:
8 u: O! ]. E7 P$ v4 aCandidate must:
        Hold BSEE (MS preferred).
$ L7 K, ~3 h. ~4 B5 Z5 k. H9 b& m. T9 w        Have minimum of 3 years hands-on experience in full flow IC back-end physical design and verification
5 c. U2 |4 t( d# r, G- y        Be able to complete block and chip level tapeout quality LVS and  LVS and DRC.
1 g* l/ ^, H1 w! F. `, `        Have the ability to independently identify and resolve design, tool, and flow problems.
" @5 M* n  [, \& v* n4 P        Have related timing and physical concept.
$ U" I' L* d  q" N        Be able to design and implement physical design strategies and methodologies for deep submicron designs.
        Familiar with EDA tools.
  w* d, N0 V, c" [0 b3 {: S: R) c        Familiar with Linux environments.  

  N( n5 ?) L2 \+ oAny of the following is beneficial:
        STA constraint design
% W6 q2 a7 s) g( O: m       Equivalence checking ?RTL to gates, and gates to gates.

ranica

数字芯片设计工程师（DFT/综合）

公      司：A mobile chipset semiconductor company
& Y( U/ ~; S1 N2 t工作地点：上海

+ v, t# i3 S; W; M# b) \职位描述：
8 k4 H1 f& T, n* a) k) {5 t1、To provide and support SYN&DFT work for several projects in parallel  
. Q5 Y. o$ I' \, I6 v2、Run block level implementation for each project, include synthesis, DFT and LEC
3、Support block level physical evaluation  
4、co-work with designer and provide block level SDC file
2 l8 _* l+ W- h, P  M8 Q5、co-work with Back-end team for timing signoff

职位需求：
& G8 @/ d1 d# M2 w' R1. 了解集成电路设计的基本流程
2. 相关Synthesis, formal check 和DFT的工作经验。(3A, 3B, 3C精通一项即可)
3A. 有超过2～3个项目的synthesis 经验， 用过RTL compiler且熟悉timing的相关知识  
) ~  k% z& }( s7 @# M, @6 X) ^3 V" O% p3B. 有超过2～3个项目的formal check经验，熟悉CPF的low power flow
4 p' K  m8 t- a: Z% U6 c% w3C. 有超过2～3个项目的DFT insertion经验， 用过Mentor DFT的优先考虑
3. 具有良好的英语阅读和书写能力。

tk02561

西班牙巴賽隆納--(美國商業資訊)--eASIC Corporation：

; `4 Z1 V2 c, y7 F7 T人物：

* i( ~2 I3 k. y  C$ n, h7 v領先的單光罩自適應ASIC設備供應商eASIC Corporation將由eASIC無線業務主管Christian Lanzani博士擔任代表，負責整體無線策略，包括無線存取、去程傳輸(fronthaul)連線、基頻處理和回程傳輸解決方案。

事件：

" i% b( v7 g5 A& G0 U; j; q) beASIC將作為聯合贊助商參加Wi-Fi世界高峰會、去程傳輸暨C-RAN高峰會(Wi-Fi World Summit & Fronthaul & C-RAN Summit)，展示C-RAN去程傳輸在部署方面的挑戰，提供eASIC解決方案的細節。展示過程將包括無線存取、CPRI over OTN轉換器和基頻集區，包括L1硬體加速的使用案例。

時間：2014年10月29日，週三
地點：西班牙巴賽隆納赫斯珀裡亞塔樓酒店(Hesperia Tower Hotel)
% Q' W! Q$ ]; [' [* b9 `0 {
如需瞭解有關eASIC Corporation的更多資訊，請造訪www.easic.com。Wi-Fi世界高峰會、去程傳輸暨C-RAN高峰會細節可以從以下網址獲得：http://wifiworldsummit.com/。

關於eASIC
) O1 ~. n- A; Q) m; c1 V
& s9 X" z' c  [2 H; }9 [eASIC是一家無晶圓廠半導體公司，提供突破性的單光罩自適應ASIC設備，旨在顯著降低客製化半導體設備的整體成本和縮短投產時間。使用通孔層客製路由的專利技術實現了低成本、高性能和快速周轉ASIC及單晶片系統設計。這種創新構造使eASIC能夠提供前期成本顯著低於傳統ASIC的新一代ASIC。eASIC Corporation是一家私人公司，總部位於加州聖塔克拉拉。投資人包括Khosla Ventures、Kleiner Perkins Caufield and Byers (KPCB)、Crescendo Ventures、希捷(Seagate Technology, NASDAQ:STX)和Evergreen Partners。如需eASIC的更多資訊，請造訪www.easic.com。

CoCo3646

Asic 的利基市場和 Fpga的利基市場 各有千秋.

fgg633