|
Junior Physical Design Engineer0 R6 l7 D; l/ _, f
~6 ^* d$ K& p) `& X3 K3 F公 司:A famous IC company
7 Z: |( P! ^& ~, y- N) W$ m& X7 T0 W工作地点:北京
$ i9 L$ n' N2 Y; r& T8 M2 e7 B9 U: W7 z: |) c, v" h
Position Tasks, Duties and Responsibilities " s+ i& z. d& b6 J- I
The ASIC Physical Design Engineer will: 7 Z5 p" K5 j* z0 f: G
Complete third party IP integration and ensure vendor guidelines are followed. % T0 q! H/ M" P6 c
Responsible for physical verification (DRC/LVS). ' C: ] O0 d4 N; f. G) `
IO ring design, fullchip floorplan. $ d4 y: b& N( K( F, x, g
Block level implementation. ]% M, y1 a# N4 x; Q' m. o% F
Work with front-end engineers to resolve problems and achieve design closure. ; L* Q5 o; _/ d! K
8 h) Q2 A% L" u$ b
Candidate Qualifications:
3 \/ q. l/ K5 _, f$ X0 N( N" c& cCandidate must: : \! }( Y* U1 t! e2 o
Hold BSEE (MS preferred).
* \$ X" ^/ r% m2 s4 w% Y; L Have minimum of 3 years hands-on experience in full flow IC back-end physical design and verification
- m, i8 t! `0 `5 F Be able to complete block and chip level tapeout quality LVS and LVS and DRC. 6 z" l5 Z1 b" M0 R* L9 V: w/ }7 I
Have the ability to independently identify and resolve design, tool, and flow problems. , U. L" [. E/ ~+ |) M
Have related timing and physical concept. % u! V- A3 \ n3 a
Be able to design and implement physical design strategies and methodologies for deep submicron designs.& H* z1 ^- v: X6 ]% X- |* U- `
Familiar with EDA tools.
& T1 J# o) `% ^9 T1 ` Familiar with Linux environments. % `' s, b4 r% d5 V
& U: H" ~/ F- V/ y4 s0 s
Any of the following is beneficial:
1 ]; j }6 j; N3 S* E6 I0 T& W STA constraint design % ` z: K) F# j6 z1 R8 ^. ^8 b2 }
Equivalence checking ?RTL to gates, and gates to gates. |
|