ASIC設計工程師如何保住飯碗？

chip123 · 發表於 2006-8-8 11:33:38

ASIC vs. FPGA？ASIC工程師如何時刻緊跟技術發展的腳步？

ASIC設計工程師如何才能保住飯碗？
上網時間 : 2006年08月07日

當大多數公司依然在使用ASIC設計時，一種新的設計模式正興起──即採用FPGA的設計方法；這種可程式設計方式對硬體沒有過多要求，而且能夠幫助設計業者避免ASIC帶來的成本增加。但是FPGA設計卻在其它方面增加了成本，例如電能消耗。
0 k$ B% g8 W% s! E
6 I. h$ `) j2 Q9 G% X8 ]2 B. r對於任何一個工程師來說，他們的職業目標都是要決定選擇哪種設計途徑：ASIC還是FPGA？並在選好之後將注意力集中在提高專業技能上。
8 m( G- [5 q: C# ~5 Y7 H$ E1 U2 |# b! \2 j& A7 x& E
工程設計正成為一門合成性的職業。在我剛入行時，它是一門手藝，一種藝術。現在它已經成為了一門科學，在我們建造更為複雜的系統的時候，這門科學的工具也越來越銳利。工程師必須時刻緊跟技術發展的腳步。

fgg633 · 發表於 2015-7-23 21:32:34

CoCo3646 · 發表於 2015-2-23 20:44:05

Asic 的利基市場和 Fpga的利基市場各有千秋.

tk02561 · 發表於 2014-10-29 08:13:11

西班牙巴賽隆納--(美國商業資訊)--eASIC Corporation：

人物：

領先的單光罩自適應ASIC設備供應商eASIC Corporation將由eASIC無線業務主管Christian Lanzani博士擔任代表，負責整體無線策略，包括無線存取、去程傳輸(fronthaul)連線、基頻處理和回程傳輸解決方案。

事件：

eASIC將作為聯合贊助商參加Wi-Fi世界高峰會、去程傳輸暨C-RAN高峰會(Wi-Fi World Summit & Fronthaul & C-RAN Summit)，展示C-RAN去程傳輸在部署方面的挑戰，提供eASIC解決方案的細節。展示過程將包括無線存取、CPRI over OTN轉換器和基頻集區，包括L1硬體加速的使用案例。

時間：2014年10月29日，週三
地點：西班牙巴賽隆納赫斯珀裡亞塔樓酒店(Hesperia Tower Hotel)

如需瞭解有關eASIC Corporation的更多資訊，請造訪www.easic.com。Wi-Fi世界高峰會、去程傳輸暨C-RAN高峰會細節可以從以下網址獲得：http://wifiworldsummit.com/。

關於eASIC

eASIC是一家無晶圓廠半導體公司，提供突破性的單光罩自適應ASIC設備，旨在顯著降低客製化半導體設備的整體成本和縮短投產時間。使用通孔層客製路由的專利技術實現了低成本、高性能和快速周轉ASIC及單晶片系統設計。這種創新構造使eASIC能夠提供前期成本顯著低於傳統ASIC的新一代ASIC。eASIC Corporation是一家私人公司，總部位於加州聖塔克拉拉。投資人包括Khosla Ventures、Kleiner Perkins Caufield and Byers (KPCB)、Crescendo Ventures、希捷(Seagate Technology, NASDAQ:STX)和Evergreen Partners。如需eASIC的更多資訊，請造訪www.easic.com。

ranica · 發表於 2014-7-31 12:31:20

数字芯片设计工程师（DFT/综合）

公    司：A mobile chipset semiconductor company
工作地点：上海

职位描述：
1、To provide and support SYN&DFT work for several projects in parallel
2、Run block level implementation for each project, include synthesis, DFT and LEC
3、Support block level physical evaluation
4、co-work with designer and provide block level SDC file
5、co-work with Back-end team for timing signoff

职位需求：
1. 了解集成电路设计的基本流程
2. 相关Synthesis, formal check 和DFT的工作经验。(3A, 3B, 3C精通一项即可)
3A. 有超过2～3个项目的synthesis 经验，用过RTL compiler且熟悉timing的相关知识
3B. 有超过2～3个项目的formal check经验，熟悉CPF的low power flow
3C. 有超过2～3个项目的DFT insertion经验，用过Mentor DFT的优先考虑
3. 具有良好的英语阅读和书写能力。

innoing123 · 發表於 2014-6-24 11:57:06

Junior Physical Design Engineer
公    司：A famous IC company
工作地点：北京

Position Tasks, Duties and Responsibilities
The ASIC Physical Design Engineer will:
      Complete third party IP integration and ensure vendor guidelines are followed.
      Responsible for physical verification (DRC/LVS).
      IO ring design, fullchip floorplan.
      Block level implementation.
      Work with front-end engineers to resolve problems and achieve design closure.

Candidate Qualifications:
Candidate must:
      Hold BSEE (MS preferred).
      Have minimum of 3 years hands-on experience in full flow IC back-end physical design and verification
      Be able to complete block and chip level tapeout quality LVS and  LVS and DRC.
      Have the ability to independently identify and resolve design, tool, and flow problems.
      Have related timing and physical concept.
      Be able to design and implement physical design strategies and methodologies for deep submicron designs.
      Familiar with EDA tools.
      Familiar with Linux environments.

Any of the following is beneficial:
      STA constraint design
   Equivalence checking ?RTL to gates, and gates to gates.

amatom · 發表於 2014-6-20 09:03:13

Senior Digital Design Engineer

公司：A leading semiconductor company
工作地点：香港

Job Responsibilities:
Perform logic design, RTL coding, design verification, logic synthesis, DFT and static timing analysis
Develop verification environment and coverage closure
Support wafer level testing and silicon evaluation
Prepare technical documents

Job Requirements:
B.Sc or above in Electronic Engineering or equivalent. Applicants with postgraduate degree would be considered as an advantage
5 Years or above of solid experience in one or more of the following areas: Verilog-based logic design and synthesis, constrained random testbench with System Verilog & UVM, assertion based design verification or circuit-level SPICE simulations
Knowledge of SoC and embedded system.
Knowledge of scripting languages such as Perl, TCL and Make
Candidate with less experience will be considered as Digital Design Engineer

ranica · 發表於 2014-6-19 09:42:41

Sr. ASIC Design Engineer (encoder/decoder)

公    司：a leading developer of advanced digital imaging solution
工作地点：上海

Position Overview: The candidate will join a team of  highly competent ASIC designers involved in design, verification, and implementation (ASIC) of advanced platform for XX''s future generation multi-media products.

主要职责 (70%)
In-depth knowledge of TV encoder and decoder design. Good understanding of TV system design.
Proficiency on digital filter algorithms and hardware implementation.
Development and verification of complex IP module, integration of the IP module into the Soc devices, top-level design handling, system level testing.
Participate in the FPGA platform development and lab debugging

其他职责 (30%)
Participate in block level architecture design Assisting embedded FW development.
职位要求
岗位资格
经验/技能
1. Strong knowledge of TV technologies, knowledge of image signal process and CCTV system is a plus
2. Strong knowledge of ASIC design flow. Can define Micro-architecture of the IP module and /or sub-blocks. And able to write detailed engineering specifications.
3. Good communication skills, especially in technical writing and reporting;
4. Self-motivated and ability to excel in a team environment.

教育
MSEE/CE with 3+ years of industry experience

ranica · 發表於 2014-6-19 09:41:01

Junior Physical Design Engineer

公    司：A famous IC company
工作地点：北京

Position Tasks, Duties and Responsibilities
The ASIC Physical Design Engineer will:
      Complete third party IP integration and ensure vendor guidelines are followed.
      Responsible for physical verification (DRC/LVS).
      IO ring design, fullchip floorplan.
      Block level implementation.
      Work with front-end engineers to resolve problems and achieve design closure.

Candidate Qualifications:
Candidate must:
      Hold BSEE (MS preferred).
      Have minimum of 3 years hands-on experience in full flow IC back-end physical design and verification
      Be able to complete block and chip level tapeout quality LVS and  LVS and DRC.
      Have the ability to independently identify and resolve design, tool, and flow problems.
      Have related timing and physical concept.
      Be able to design and implement physical design strategies and methodologies for deep submicron designs.
      Familiar with EDA tools.
      Familiar with Linux environments.

Any of the following is beneficial:
      STA constraint design
   Equivalence checking ?RTL to gates, and gates to gates.

mister_liu · 發表於 2014-6-12 10:46:55

Junior Physical Design Engineer

公    司： famous IC company
工作地点：北京

Position Tasks, Duties and Responsibilities
The ASIC Physical Design Engineer will:
      Complete third party IP integration and ensure vendor guidelines are followed.
      Responsible for physical verification (DRC/LVS).
      IO ring design, fullchip floorplan.
      Block level implementation.
      Work with front-end engineers to resolve problems and achieve design closure.

Candidate Qualifications:
Candidate must:
      Hold BSEE (MS preferred).
      Have minimum of 3 years hands-on experience in full flow IC back-end physical design and verification
      Be able to complete block and chip level tapeout quality LVS and  LVS and DRC.
      Have the ability to independently identify and resolve design, tool, and flow problems.
      Have related timing and physical concept.
      Be able to design and implement physical design strategies and methodologies for deep submicron designs.
      Familiar with EDA tools.
      Familiar with Linux environments.

Any of the following is beneficial:
      STA constraint design
   Equivalence checking ?RTL to gates, and gates to gates.

ranica · 發表於 2014-6-4 09:13:19

Senior Digital Design Engineer

公司：A leading semiconductor company
工作地点：香港

Job Responsibilities:
Perform logic design, RTL coding, design verification, logic synthesis, DFT and static timing analysis
Develop verification environment and coverage closure
Support wafer level testing and silicon evaluation
Prepare technical documents

Job Requirements:
B.Sc or above in Electronic Engineering or equivalent. Applicants with postgraduate degree would be considered as an advantage
5 Years or above of solid experience in one or more of the following areas: Verilog-based logic design and synthesis, constrained random testbench with System Verilog & UVM, assertion based design verification or circuit-level SPICE simulations
Knowledge of SoC and embedded system.
Knowledge of scripting languages such as Perl, TCL and Make
Candidate with less experience will be considered as Digital Design Engineer

ranica · 發表於 2014-3-7 13:12:49

职位要求
?Extensive hands-on experience in the development of WiFi baseband IC design. The candidate must have at least 8-years development experience on WiFi 802.11 a/g/b including minimum 3 years on 802.11n/ac.
?Deep knowledge and good understanding of: digital communication theory, information theory; specifically on: equalization, Fourier transform, spatial-temporal coding, linear and maximum-likelihood estimation, Viterbi decoding, frequency/ timing estimation and calibration, automatic gain control, transmitter beam forming, diversity combining, and their high-speed DSP/digital implementation.
?Extensive experience with RTL programming languages.
?Experience with verification methodologies and tools and advanced complex RTL/C test-bench developments. The familiarity with UVM environment is a plus.
?Experience with developing algorithms in C, C++, and Mat lab.
?Experience with scripting language such as Perl, Python.
?Must have experience with lab testing and characterization of digital sub-systems.
?Candidate must have strong English communication skills with willingness to interact with various groups within the company.
?Experience with physical design flows, tools, methodologies, and development of timing constraints is a plus.
?Familiarity with flows and tools for co-simulation of RTL and C models is a plus.
?Familiarity with testing and integration of RF and baseband systems in the lab is a plus.
?Experience with implementation of calibration modules for RF/Analog blocks is a plus..
?Typically requires a Master degree and 8 years of experience or a PhD and 5 years, in VLSI/ASIC architecture design or ASIC implementation of digital signal processing function.

ranica · 發表於 2014-3-7 13:12:33

Sr. Staff to Principal Engineer/Mgr
公司：A famous IC company
工作地点：上海

Job description
The candidate will be responsible for the architecture and ASIC design and co-verification of various 802.11 wireless baseband IPs within current and next generation wireless products. The candidate will work within the local DSP/digital development team and closely with system/simulation/verification/RF engineering teams in US to develop and implement DSP/digital blocks to build WiFi IPs.

Job responsibilities includes: spec development and design of DSP/digital blocks, developing co-verification platforms, performing simulations, and solving integration and testing problems during the development, characterization, and production stages of the product. Successful candidate must have the ability to communicate with engineers of various backgrounds: systems, software, digital hardware, RFIC design, and verification

ranica · 發表於 2014-3-6 14:28:52

数字IC设计工程师
公司：A famous IC company
工作地点：上海

岗位职责：
负责各种IP（图形图像接口、图形图象处理、视频编解码、DDR存储接口、Flash接口、USB接口等）的设计、时钟复位模块的设计或者SOC相关的集成设计、系统设计、架构设计。

职位要求：
1、硕士及以上学历，电子、通信、计算机或微电子专业；
2、熟练掌握Verilog、SystemVerilog等语言的编程，有扎实的数字电路基础；
3、有1~2年的相关工作经验；
4、具有较强的学习能力、沟通能力和良好的团队合作精神；
5、在以下相关的模块或接口（其中之一）有一定的工作经验：图形图像接口、图形图象处理、视频编解码、DDR存储接口、 Flash接口、USB接口等
6、有大型SOC芯片的研发经验者优先考虑。

ranica · 發表於 2014-3-6 14:28:16

资深数字IC设计工程师（图形图像方向）
公司：A famous IC company
工作地点：上海

岗位职责：(图形图象处理和视频编解码方向)：
1、根据市场需求和芯片定位，参与并带领团队完成图形图像处理或视频编解码等复杂IP的设计验证和交付；
2、对项目进度和质量负责，组织具体技术难点或紧急任务的讨论和攻关，协调其他团队共同完成SPEC的制定和收敛；

岗位要求：
1、硕士及以上学历，电子、通信、计算机或微电子专业；
2、有至少两年以上图形图像或视频编解码等领域的IP设计经验；
3、具备丰富的图形图像处理或视频编解码等相关领域的系统知识
4、具有扎实的数字芯片设计基础，熟悉IC设计的整个流程；
5、具有良好的沟通能力，较强的协调能力，以及团队合作意识；
6、有团队管理经验者优先考虑；

ritaliu0604 · 發表於 2014-1-15 09:44:14

数字芯片设计工程师（DFT/综合）
公    司：A mobile chipset semiconductor company
工作地点：上海

职位描述：
1、To provide and support SYN&DFT work for several projects in parallel
2、Run block level implementation for each project, include synthesis, DFT and LEC
3、Support block level physical evaluation
4、co-work with designer and provide block level SDC file
5、co-work with Back-end team for timing signoff

职位需求：
1. 了解集成电路设计的基本流程
2. 相关Synthesis, formal check 和DFT的工作经验。(3A, 3B, 3C精通一项即可)
3A. 有超过2～3个项目的synthesis 经验，用过RTL compiler且熟悉timing的相关知识
3B. 有超过2～3个项目的formal check经验，熟悉CPF的low power flow
3C. 有超过2～3个项目的DFT insertion经验，用过Mentor DFT的优先考虑
3. 具有良好的英语阅读和书写能力。

globe0968 · 發表於 2013-11-29 13:38:21

IC PM
公    司：A famous European IC company
工作地点：上海

Roles and Responsibilities
1. Manage ASIC design project according to product development process
   - Coordinate the different resources to deliver the ASIC product in time and with good quality
   - Responsible for the communication of the whole project team
   - Participates and drives internal review of each development phase and make proper justification
   - Develop and manage project schedule, resource, communication and critical path
   - Identify risk and develop mitigation plan with the project team
2. Closely work with IC manufacturing and testing / qualification to drive the ASIC products into mass production in time and with good quality
3. Work with the financing and control the project budget

Qualification Requirement
- Master degree or above in Device Physics, Electrical/Electronics Engineering or equivalent
- 4+ years experience in the semiconductor industry in relevant R&D departments.
- Preferred to have at least 1 successful tape-out experience as project manager
- Knowledge of ASIC Design from front-end to back-end (Analog design, RTL, Synthesis, STA, floor-plan, P&R, package, testing, etc.)
- Basic leadership of team for allocation of tasks
- Management experience with subcontractors
- Good English, excellent communication skills and team spirit oriented
- Self motivated, strong communication and interpersonal skills

ranica · 發表於 2013-11-28 09:28:03

数字芯片设计工程师（DFT/综合）

公    司：A mobile chipset semiconductor company
工作地点：上海

职位描述：
1、To provide and support SYN&DFT work for several projects in parallel
2、Run block level implementation for each project, include synthesis, DFT and LEC
3、Support block level physical evaluation
4、co-work with designer and provide block level SDC file
5、co-work with Back-end team for timing signoff

职位需求：
1. 了解集成电路设计的基本流程
2. 相关Synthesis, formal check 和DFT的工作经验。(3A, 3B, 3C精通一项即可)
3A. 有超过2～3个项目的synthesis 经验，用过RTL compiler且熟悉timing的相关知识
3B. 有超过2～3个项目的formal check经验，熟悉CPF的low power flow
3C. 有超过2～3个项目的DFT insertion经验，用过Mentor DFT的优先考虑
3. 具有良好的英语阅读和书写能力。

ranica · 發表於 2013-11-26 09:32:17

ASIC Digital Verification Engineer

公    司：A mobile chipset semiconductor company
工作地点：上海

Responsibilities:
  Make verification plan for one module or whole chip.
  Build up and maintain module-level and chip-level verification environment
  Verify ASIC digital design based on case list, and output verification report.
  Also responsible for lint checking and formal verification.

Qualifications:
  Proficiency in logic verification.
  Experience with Verilog logic design language.
  Experience with high-level verification languages such as System Verilog, System C, Vera or Specman e language.
  Experience with UNIX/Linux simulation tools such as IUS or VCS.
  Experience with C and C++ is a plus.
  Experience with C_SHELL, TCL or PERL is a plus.
  Experience with UVM, OVM or VMM is a plus.
  Good knowledge of SOC design is a plus.
  Good knowledge of software design is a plus.
  Self-motivated and good team player.
  MSEE or BSEE with 2+ years.

tk02561 · 發表於 2013-11-19 09:00:29

ASIC工程师
公    司：High-technical IC supplie with commercial FPGA intellectual property
工作地点：北京

职位描述
1.微电子相关专业硕士学历, 3+年ASIC前端工作经验（不含在校、实习）;
2.熟悉并参与过ARM或MIPS等常用SOC架构的设计、应用,对SOC架构及常用外设的工作原理有深入理解。
3.精通verilog语言，能够独立完成verilog module design，拥有良好编程习惯codingstyle。
4.能够独立完成单元级仿真，在系统仿真中承担部分工作。
5.至少1次成功流片经验。
6.对synthesis、sta、dft等有一定了解。
7.良好的团队合作精神

职位要求
全部或部分满足以下条件者优先考虑：
1.有在大型asic公司工作经验，深入理解其企业文化。
2.熟悉验证方法学;熟练使用SystemVerilog等专用语言进行验证平台的搭建和维护。对Testcase规划、覆盖率分析、门级仿真、ATE testpattern产生等有实践经验和深入理解。
3. 丰富的fpga emulation经验，能熟练进行板级debug，编写调试简单driver。
4．对芯片系统架构有一定理解，能进行子系统级别的独立规划设计。对以下知识中的至少2种有实际经验：
ARM/MIPS/8051 CPU及其架构,
AMBA(AXI/AHB/APB) 总线、OCP,
USB(3.0/2.0/1.1,
NAND/Nor Flash/S-flash controller
DDR（2.0/3.0）controller/PHY
low power design,
chip level clock/reset generation and control,
SD card controller, SATA,sim card
soc基本外设 (SPI/ GPIO/timer/WDT/I2S(SSI)/I2C/UART),
Ethernet,
JTAG, etc.

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ASIC Corporation將展示節能、高頻寬效率的C-RAN解決方案

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