ASIC設計工程師如何保住飯碗？

ranica

招聘公司：A famous IC company
招聘岗位：Asian Technical ASIC leader
8 G' }& L8 I8 J# w+ {9 q+ A  n0 i工作地点：Shanghai

' i0 `7 ?' S  P5 t; o岗位描述：
Responsibilities - To build designing team in Asia. The number of this team is 30-50 engineers on the 3rd year supporting 100M business in Asia - To provide direct technical customer support and build strong customer relationships - To work with the sales team for our business in Asia - To communicate with different designing team worldwide
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职位要求：
8 W' m% h: w% cTechnical Qualification (15+ years)
• Has an excellent grasp of the backend ASIC methodology and flow from RTL to Tapeout in either prior technical contribution roles or technical management or lead roles. This covers o Third-party IP selection and integration o IO ring and package (flipchip, wirebond) co design o Analog IP selection and integration o High speed interface (DDR2/DDR3, Serdes) integration and analysis o Hierarchical physical implementation using a mainstream toolset such as Magma, Synopsys or Cadence o DFT implementation including at speed memory bist and repair and scan compression o IP test considerations such as high speed loop back tests and analog test inmtgeration o Timing closure and sign-off o Tapeout sign-off
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• Any specialty and experience in ASIC methodology and flow will be highly desirable. Example(s): o Deep expertise with any mainstream ASIC tools or specialized tools along the flow o Low power flow with IPs and implementation techniques o Complex SOC implementation with flipchips and large number of on chip Serdes o Complex mixed signal chip integration with significant amount of on chip analog IPs o Special design and packaging such as MCMs and 3DICs • Ability to contribute in a lead technical or advisory role to key R&D programs in improving or differentiating ASIC flow in power, performance area or cost.

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• Experience with RTL design and verification and product design in any market segment in either technical or management role in a big plus
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  J: p& D1 h/ O2 |! G: y% h# |• Experience with Tapeout to full product production and rollout including proto bring-up and debug/validation process, characterization, qualification and supply chain management is high desirable. Management and Business Qualification

! F/ Q" J+ V# O; i! v• Direct experience in ASIC technical project management is highly desirable • Has strong leadership qualities that can support eSilicon GM of Asia to setup and grow a local ASIC technical team
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$ E5 V" o; l" M$ t, u• Experience in leading and managing global projects and internal engineering or product teams is highly desirable

• Experience in interfacing with third-party suppliers within the silicon supply chain (IP suppliers, design service firms, EDA suppliers, backend foundry, assembly and test operations) is a highly desirable

• Experience with key customer interfaces in ASIC support role or other partnering or supporting roles is highly desirable • Well connected in business communities, including at VCs, across the Asian region is highly desirable
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  E2 ?- Z  }; `! d6 U9 ]6 f• Awareness of technical developments in the segments which are dominant across Asia so that we can better position ourselves when competing for business is highly desirable
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• A strong technical leader who will be persuasive in selling our capabilities to high end Asian customers
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' ]9 b8 H1 I' W- x% V: r• Has the ability to understand our limitations, but also able to work internally to mitigate the effect of those, so that they do not impede our ability to win business nor allow us to screw-up after winning deals. A strong team player who is flexible, dynamic and capable to partner with other functions as we are growing the Asian business aggressively
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% @  ?- P& q. o• Capable of putting together and giving presentations at high level shows so that we are perceived as a technical leader

ranica

招聘公司：A famous IC company
* |$ F, N4 q5 @1 S4 S; U招聘岗位：SOC FPGA engineer
工作地点：Beijing

岗位描述：Job Description:

/ r0 r4 f7 ]4 O. ]4 j · This position should perform Pre-silicon (FPGA) implementation of the ARM based SoC chips for mobile devices
) N+ @2 `* W; ~· Support FPGA user design, testing and troubleshooting · Engage FPGA prototyping domain technical skill improvement and engineering process improvement Responsibilities:
· Define FPGA prototyping methodology and strategy · Draft FPGA design spec and development plan
2 X* C$ n( x5 M  z· Keep tracing and improving FPGA validation technology, methodology, flow and define/improve the engineering processes
· Develop FPGA DV and sanity check test case · Implement FPGA integration based on FPGA prototyping strategy
· Experience in Logic design with high-level description language like VHDL/Verilog. It will be an added advantage if the code were written to be FPGA friendly.

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· Understand the custom requirements of a Complex ARM based FPGA design which includes: ARM boot-up requirement, complex clock tree scheme, RAM/ROM inferring, and some basic analog blocks/interface like PLL. Experience with Radio RF will have an added advantage. · Ability to translate ASIC design into FPGA by translating clocks, RAM/ROM and other essential analog block to equivalent FPGA device components and requirements · Familiar with Synthesis with Synplify with clear understanding the interface/timing constraints, and ability to clean all timing issues before P&R phase. · Familiar with FPGA tool to ensure bit file generation fits the size, performance and I/O of the design. · Understand FPGA board requirements and co-design with HW team · Responsibility to verify the netlist so that it will be fully functional when downloaded on FPGA board.
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职位要求：
Requirements: · Candidates must have at least 4-6 years of relevant experience. · Master’s/Bachelor’s Degree in Electrical/Electronic Engineering with an emphasis in IC design · Must be familiar with Xilinx and Altera devices and their tools · Must be familiar with Synplify synthesis tool · Must be able to understand and debug FPGA boards. · Must understand tcl/shell scripts to construct or modify constraints files. · Knowledge about complete life cycle of IC and FPGA development. · Knowledgeable in digital High Speed GHz frequency design and RF Radio is an added advantage · Knowledgeable of ARM based SoC design is an advantage · Good written and communication skills · Experience in WLAN, BlueTooth, GPS, NFC, FM or Modem (LTE, TD-SCDMA, WCDMA) SoC/IP design is preferred. · Experience with muli-site/multi-team/multicultural cooperation is preferred

ranica

招聘公司：A famous IC company
7 j+ R) C6 N. ]' n3 @& r4 e8 R$ F6 F招聘岗位：ASIC Physical Design Engineer
1 \, J5 @/ F2 R. E( B4 J工作地点：Shanghai
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岗位描述：
! G0 D# @# [( g1 ~% T4 r- owning, and maintaining P & R scripts for block gate netlist to GDSII - P & R, extraction, Power IR, EM of block level and Physical verification - Work with front end engineer for timing closure activities

职位要求：
* q% _9 U: g* e( n8 s: b9 Z8 v, H• BSEE is required • 3+ years of ASIC/SoC Physical Design; floor planning, power grid customization, P&R, CTS, DRC, LVS, etc... • Experience driving CTS to meet requirements • Experience with either one of P&R tools; Cadence EDI, or Synopsys IC Compiler • Proficiency using TCL, Perl and make scripting

ranica

招聘公司：A Fabless IC design Company
招聘岗位：SenDigital IC Design Engineer
工作地点：Suzhou

岗位描述：
职位描述： 1、参与芯片架构设计； 2、负责数字电路的模块和微结构的设计及RTL设计； 3、进行电路仿真，协助芯片的模块级和系统级验证； 4、芯片电路综合、时间收敛、面积优化、功耗分析、形式验证、板上调试等；
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职位要求：
( P- r: v, H# X3 c( y2 F+ v任职要求： 1、通信，信号信息处理，微电子等电子相关专业博士或硕士三年以上工作经验； 2、1-2年CMOS数字逻辑电路设计经验； 3、熟悉数字集成电路前端和后端设计流程，熟悉Verilog等硬件电路设计语言； 4、熟悉数字逻辑电路设计的相应EDA工具 5、有商业芯片流片经验者优先； 6、要求良好的沟通能力和团队合作精神，工作积极主动，踏实好学。

ranica

招聘公司：a start-up company with high performance bletooth and Wifi technology
招聘岗位：ASIC Design Manager
$ A7 u: S5 W& F3 ^工作地点：Shanghai

/ F9 A* ?2 s' j; M8 ~* t岗位描述：
& q, S6 M# \! IResponsibilities: 1. Responsible for architecting each product, and for overseeing architecture definition, block partition, HDL code, synthesis, logic verification, system verification (FPGA), analog IP design, and static timing analysis for pre and post layout. 2. Overseeing floor planning and place & route of the chip, including IP block integration 3. Manage a group of engineers to get the product successfully developed.
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! [' n- j; C; m. a" d职位要求：
Requirements: 1. 5+ years experience as an ASIC/logic designer. 2. Must understand chip design from architecture down to GDS. 3. Must have good managerial skills. 4. Must be a good team worker, possess a good personality. 5. BS/MS in EE or higher.

ranica

招聘公司：A famous IC company
招聘岗位：ASIC - Director of ASIC Engineering
工作地点：Shanghai
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岗位描述：
5 b" m! A, m1 n9 P. LJob Description Director of ASIC will lead a team of ASIC engineers and own the development activity of the ASIC portion of one or more ***’s SOC products. The responsibilities include building a world class ASIC team and a state of the art ASIC methodology to enable solid execution of the digital ASIC. The Director will interface with peers in Marketing, Systems, RFIC and Operations to ensure that *** will execute and deliver highly differentiated, low power SOC products that are market winners.

ranica

职位要求：
Required Skills Experience and Skills: A motivated self-starter, team builder and an inspiring and effective leader. Strong communication skills and ability to interface with multiple teams such as Marketing, Systems, RF/MS IC Design and Operations. Experience in communication chips (PHY and SoC) developments. Prior experiences in commercial digital ASIC development from specification, design, tape- out to characterization and production. Strong organizational skill to help with project management of complex SOCs. Drive ASIC methodology and IP and tool evaluation. Technical expertise on the entire ASIC design flow—architecture, logic design, RTL coding, verification, FPGA validation, synthesis, DFT, timing closure and physical backend leading to tape-out. Experience with low power techniques is a plus. Required Experience Education/Training: MSEE required (Ph.D. preferred), 10+ year industrial experience. 5+ years’ experience in managing ASIC teams and leading product development.

ranica

招聘公司：A famous IC company
' d0 K5 g) r5 Y- G7 Y) i6 K招聘岗位：(Senior) ASIC Design Engineer
工作地点：Shanghai
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岗位描述：
) `* H6 J1 @8 K  P% A' B+ z0 RASIC front-end engineers will be responsible for design and development of ASIC functional blocks in communications SoC products. These include building blocks for communications/DSP functions and/or System-on-the-Chip (SoC) blocks (such as CPU subsystems, I/O peripherals, and memory controllers… etc.).

2 x0 r$ @2 M5 Q" Q3 l职位要求：
* u# n' f; ^: K1. Good understanding of the whole ASIC design flow, from Micro-architecture design to silicon bring up. 2. Good understanding of modem verification methodology 3. Strong logic design/debug ability and good RTL implementation skill. 4. Ability of block/chip level synthesis and equivalence check. Can work closely with backend for physical implementation 5. Ability of C/C++ programming. Familiar with at least one script language. 6. Strong communications skills. Must be able to communicate fluently in English Following knowledge and experience are also strongly desired: 1. Good background in communication/DSP theory; 2. Knowledge in embedded MCUs and AMBA protocol; 3. Experience of working with oversea teams. Required Education and Experience • Sr. Design Engineer: BSEE required, MSEE preferred. 5+ years of hand-on design experience. • Staff Engineer: BSEE required, MSEE preferred. 8+ years of hand-on design experience.

ranica

Senior ASIC engineer
4 q! H, a5 ]( a1 z- I# r客户 a start up company with innovative technology
地点 Shanghai
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7 F- P% P1 q1 r: d4 T/ U职位要求
5 + years experience in ASIC design -> must
; O4 S2 g' Y+ T( ?; h. r· MS in Electrical Engineering (or equivalent) is a must have
4 _8 i0 C# z4 F7 a$ [· Experience with WIFI baseband/MAC or related wireless baseband technology desired -> plus
2 F, v& m& a# ~! u! S* u; S. D· System on Chip (SOC) Integration Experience, including AHB/AXI, CPU integration -> plus
: z# q2 ^: j1 `8 s+ u· Experience with interfaces such as SPI, SDIO, USB -> plus
& q* C3 Y# ?! s+ B  H* ^4 }· Working knowledge of networking protocols such as TCP/IP, 802.3, 802.11 -> plus
: T' C: h& Z$ }& z9 }* j· Must be expert in Verilog RTL language -> must
· Must be familiar with the ASIC design flow from RTL through synthesis, including the tool flow. -> must
· Verification experience – Verilog, System-Verilog, Coverage Analysis -> must for verification engineer, plus for design engineer
· FPGA emulation experience -> plus
· Chip bring-up experience, including use of Logic Analyzer and Oscilloscope for debugging -> plus
+ _1 M) M# W9 E) L- E( G· Experience with digital backend

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资深数字设计工程师
# Z: Q- _/ x/ w2 t3 p客户 A start
3 _0 Z  x  V6 S5 V( |/ J! R- Y. x地点 Shanghai

职责:
参与从产品定义到量产的整个流程。
参与芯片架构定义。
ASIC设计，RTL编程和RTL仿真。
1 e! k9 B* E  q综合和FPGA评估。
与应用测试工程师合作，提出最优解决方案。
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职位要求：
电子工程相关专业硕士毕业。
3年至5年以上RTL设计经验。
* S; o: _) }% s- z+ B/ `有音视频领域经验优先。
& c$ M% a% [  u/ w4 d; x1 x良好团队精神，学习能力强，敢于接受挑战。
必须具备RTL编程、仿真经验。
; L- k$ G0 g, R3 @& y熟悉FPGA验证优先。

ranica

资深数字设计工程师

! p% `# T) Y/ J' O6 |6 X公      司：NO.233-A start-up company
工作地点：上海

3 }% U" p; r* p8 [5 G- G职责:
参与从产品定义到量产的整个流程。
参与芯片架构定义。
ASIC设计，RTL编程和RTL仿真。
5 Q2 M5 [, y# A$ X综合和FPGA评估。
7 U/ H8 f, ?0 W7 b与应用测试工程师合作，提出最优解决方案。
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要求：
电子工程相关专业硕士毕业。
3年至5年以上RTL设计经验。
) S# ^0 p5 l! x7 n- N有音视频领域经验优先。
4 \3 T9 [0 Y1 \. s  f良好团队精神，学习能力强，敢于接受挑战。
  X( a- y0 M' T3 ~6 p- Y必须具备RTL编程、仿真经验。
熟悉FPGA验证优先。

ranica

Staff Digital Design Engineer
! Y& F: b8 H0 E) S( A公      司：NO.82-A famous IC company
2 Z% t8 J( h2 o+ u- u/ N工作地点：上海

职位描述
A worldwide leader in the design and manufacture of microcontrollers, capacitive touch solutions, advanced logic, mixed-signal, nonvolatile memory and radio frequency (RF) components. Leveraging one of the industry''s broadest intellectual property (IP) technology portfolios, be able to provide the electronics industry with complete system solutions focused on industrial, consumer, security, communications, computing and automotive markets. As a global company with 5,100 employees worldwide, she operates in more than 40 countries and has 30 design centers, including locations in Shanghai and Taipei. Her solutions enable their customers to lead the markets they serve by creating products that are more powerful, smarter, energy efficient, lower cost, and more versatile than ever before.
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Responsibilities
6 v5 C; k) y$ Q! ~* z: a' A( D• Develop ARM-based MCU/SOC products
- F2 O% Q; M9 i" H. ]职位要求
Mandatory Skills
7 [) X/ `8 [2 {6 T' e3 [+ l        Very good Verilog coding and simulation capability.
4 ^  v0 v' q5 r9 N! Q8 P2 r& ~, T Familiar with ASIC design flow, including related tool experience and skill, such as DC , conformal , formality , Tmax or PT.
1 k2 A# x0 X! ?1 v3 t/ E; x. U5 h8 N        Fluency in English and good in communication skill.
Preferred Skills
+ C2 @9 N" q6 w) o2 H        ARM-Based MCU or DSP related experience and knowledge is highly preferred.
        Understanding of embedded firmware and programming is a plus.
9 Y6 B3 c- E; B0 i" h/ G/ G        Unix/Linux shell/script programming.
) D; E, f  M$ U; {" I' L. _; zEducation
& N8 Y9 ]. n. ^( [8 y. s9 G, AMaster Degree of EE or related.
Experience
2 f$ Y; _$ r+ W6 M5 d        8+ years of design experience.
* h5 T# N1 C1 }, c        At least two years of US or Europe-based company experience.
Position: Regular
Shiftay
Location: China

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ASIC Design Manager
公      司：a provider of highly integrated semiconductor company
3 P. Q+ C9 B2 K1 @  c- x( L工作地点：北京

7 L+ X# I, ], @, w0 q, V7 V& ?' sDescription:  
5 C. T9 P; H" c: q/ YRoles & Responsibilities:
! Z/ F. _& A0 k* P( t0 y/ iIn charge of logic design from spec to tape out and bring up  
+ r4 x/ E2 g3 o5 j1 Y7 V, U+ mMicro architecture and implementation  
$ f' W9 O$ u4 ?Working on or lead logic design, simulation, validation  
Coordinate analog design, bring up and thouble shooting

Requirements:
5+ experience on IC design  
Deep knowledge and skill on ASIC design flow including RTL coding, simulation,  synthesis, timing closure, power estimation, formal validation
Deep knowledge on digital baseband or SoC design   
Master degree or higher.  
1 H  `& X# f- u$ U0 k! bIt will be plus having experience to lead and deliver ASIC project

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数字工程师
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公      司：IC设计公司
工作地点：深圳

职位要求
1、 熟悉数字电路设计流程方法及工具；
6 C! A: G. A9 \& |! C, t% S2、 精通LCD数字电路设计；
& {/ u" l5 j5 S8 m% C+ J3、 具有两年以上MIPI设计经验。

ranica

ASIC Design Engineer
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2 E9 y3 s9 Y6 F; ?. _公      司：A famous IC company
6 w/ g7 K6 h- A. c6 U; H工作地点：上海

The Role:
, o. o; J& j% O5 R3 W8 D3 |3 E' v·         ASIC design  
( L2 N; l" y; R  S7 e. H·         Work closely with the California teams
- p, z7 j8 }3 ^8 ]! m$ h·         Support chip tape out and bring up

( y* S& o5 y" ?0 t1 M  mRequirements:
  i. d& V0 ]6 G+ e/ ^; z; Q·         3+ years experience in ASIC design
& ]. Y. y# r9 ^7 P5 m·         BS in Electrical Engineering (or equivalent) is a must have, MSEE is desired
! Z4 V  U4 C9 y% g4 u( f( @& Y+ X·         System on Chip (SOC) Integration Experience, including AHB/AXI, CPU, Interface integration
·         Experience with WIFI or related wireless technology (i.e. WIMAX, 3G, LTE, etc.) is a plus
·         Experience with interfaces such as PCIe, Ethernet, DDR, USB
·         Working knowledge of networking protocols such as TCP/IP, 802.3, 802.11
, S, D* y5 z( K+ h. U0 ^7 O·         Working knowledge of C programming language
·         Experience with Medium Access protocols a plus
* c; z4 J+ c& _4 }·         Must be expert in Verilog RTL language
0 H2 T  s6 T2 L* B: l·         Must be familiar with the ASIC design flow from RTL through synthesis, including the tool flow.
" K3 d+ H: }% l3 e. q( M1 v, g: c·         Verification experience – Verilog, System-Verilog, Coverage Analysis
8 W) U2 E5 W9 s6 ^1 g·         FPGA emulation experience
7 ?6 q' \; _; X1 M4 d* n1 c' l) D·         Chip bring-up experience, including use of Logic Analyzer and Oscilloscope for debugging

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IC PM

公      司：A famous European IC company
: [* s& G3 ]$ _3 _; p7 v) ?# {: k工作地点：上海

Roles and Responsibilities   
' E9 }1 K$ x! |" Y1. Manage ASIC design project according to product development process   
     - Coordinate the different resources to deliver the ASIC product in time and with good quality  
( b0 N( w3 z% |* l' A. T     - Responsible for the communication of the whole project team  
     - Participates and drives internal review of each development phase and make proper justification  
; ]; i  P& F4 K) }# S     - Develop and manage project schedule, resource, communication and critical path  
     - Identify risk and develop mitigation plan with the project team  
2. Closely work with IC manufacturing and testing / qualification to drive the ASIC products into mass production in time and with good quality
- i, W  y9 s! I. {5 n. i3. Work with the financing and control the project budget

  c1 O- ]: }  v7 g( T9 ZQualification Requirement   
+ x- t4 o5 v1 f0 D: z  P' M- Master degree or above in Device Physics, Electrical/Electronics Engineering or equivalent  
( b  W( A% R1 K! H, N  Z. `& I- 4+ years experience in the semiconductor industry in relevant R&D departments.  
4 o4 U7 E3 l  D- Preferred to have at least 1 successful tape-out experience as project manager  
- Knowledge of ASIC Design from front-end to back-end (Analog design, RTL, Synthesis, STA, floor-plan, P&R, package, testing, etc.)  
- Basic leadership of team for allocation of tasks   
. {. S- [. z7 z+ F- Management experience with subcontractors  
- T' o. ^! o; ]+ B) f  x# q- Good English, excellent communication skills and team spirit oriented  
6 f% S" s- D6 r; [5 H, k- k- Self motivated, strong communication and interpersonal skills

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ASIC Digital Verification Engineer

+ a/ N2 \& b& O- k/ B公      司：A mobile chipset semiconductor company
工作地点：上海

Responsibilities:  
& e" F+ F# t% k8 J! o" @5 A5 U; z  Make verification plan for one module or whole chip.  
5 y5 j; A% X9 ?' V6 w$ N" ?  e  Build up and maintain module-level and chip-level verification environment  
2 j$ k2 v6 l9 T9 z/ w3 V- ^  Verify ASIC digital design based on case list, and output verification report.  
  Also responsible for lint checking and formal verification.  

Qualifications:  
  n  ?$ [4 z- N" O4 X! o  Proficiency in logic verification.  
" s2 h; P7 K/ j2 B  Experience with Verilog logic design language.  
' j9 n. b0 R! f7 G7 Y  Experience with high-level verification languages such as System Verilog, System C, Vera or Specman e language.  
( r+ E' h) h( A: D  Experience with UNIX/Linux simulation tools such as IUS or VCS.  
# _6 |5 m' @& q6 X! M  Experience with C and C++ is a plus.  
8 `. _, t) e5 W" \- Y5 ]5 a  Experience with C_SHELL, TCL or PERL is a plus.  
  Experience with UVM, OVM or VMM is a plus.  
  Good knowledge of SOC design is a plus.  
  Good knowledge of software design is a plus.  
  Self-motivated and good team player.  
! k- s% K2 |( `5 t) s  MSEE or BSEE with 2+ years.

ranica

数字芯片设计工程师（DFT/综合）
2 E6 V4 _% m, S' a  M% L
公      司：A mobile chipset semiconductor company
工作地点：上海
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  K0 K7 g, z) s* K0 M, f职位描述：
1、To provide and support SYN&DFT work for several projects in parallel  
2、Run block level implementation for each project, include synthesis, DFT and LEC
3、Support block level physical evaluation  
1 Z/ }1 N6 D- _. v8 W! i9 h7 h4、co-work with designer and provide block level SDC file
+ f% t9 O7 z/ c0 y) q" k5 L, z$ \% v% f5、co-work with Back-end team for timing signoff

  I0 Z: k% N* _职位需求：
1. 了解集成电路设计的基本流程
2. 相关Synthesis, formal check 和DFT的工作经验。(3A, 3B, 3C精通一项即可)
3A. 有超过2～3个项目的synthesis 经验， 用过RTL compiler且熟悉timing的相关知识  
3B. 有超过2～3个项目的formal check经验，熟悉CPF的low power flow
3C. 有超过2～3个项目的DFT insertion经验， 用过Mentor DFT的优先考虑
3. 具有良好的英语阅读和书写能力。