身為IC設計者，我面對的最大壓力？

chip123 · 發表於 2006-7-12 14:43:07

8月中旬有兩天整以「如何搭起設計除錯與結果分析之間的橋樑？」為主題的IC設計研討會，如果部分會員們有意參加，在那之前何妨先來討論討論如何？

http://www.maojet.com.tw/Events/index.asp?Page=1

引言回覆:
IC 設計的大小與複雜度，對於產出良率與產品上市時間影響甚鉅。設計者除了要面對更為嚴苛的設計工作之外，還必須同時承受時間上的壓力。

即使運用現有的分析工具，在設計除錯與結果分析之間，還是隱約存在一道看不見的鴻溝。就算是針對 Spice 模擬工具的需求，將解決方案與看起來 “還算不錯” 的波形分析結合在一起，依舊不能有效消弭這段差距。完美整合的 “最頂級” 解決方案，不僅使用容易，更可支援以下三類資料的分析作業：模型建立（Modeling）過程中所描述之模擬、硬體量測，以及系統階層。

_________________
鏈結IC創新價值鏈，擴大IT市場同心圓
論壇需要大家踴躍的參與才能不斷的發展
休息是為走更長遠的路，回覆是發表的原動力

ranica · 發表於 2014-7-29 11:21:23

Senior Engineering Manager

公    司：One world top EDA company
工作地点：北京

Position Description
1. World’s leading design companies rely on xx technologies to deliver the latest design innovations in consumer,
mobile and enterprise electronics. We are looking for a strong software engineering leader to join our team and contribute to the continued growth and success of the company’s flagship products, including ADE and AMS Designer.
2. In this high-impact career opportunity you will be responsible for delivery of cutting-edge features in mixed-signal simulation and the Virtuoso environment, including technology leadership, team development and people management.
3. You will also work with a cross-functional team in Beijing and North America to ensure that our software is developed, tested, and documented with high quality.

Position Requirements
Requirements:
1. Experience managing software development teams in the EDA or related industry
2. Successful delivery of software products over multiple release cycles
3. Proficiency with build and version-control systems
4. Strong software engineering skills in C/C++ and familiarity with Linux/Unix development
5. Excellent written and oral English communication skills

Preferred skills:
1. Prior experience with analog, digital or mixed-signal simulation using SPICE, Spectre and Verilog languages
2. Exposure to the Virtuoso environment or other electronic design platforms

Education:
B.S. or higher in engineering, computer science or related field.

ranica · 發表於 2014-5-21 09:33:33

DIP Application Engineer
公    司：One world top EDA company
工作地点：上海

Responsibilities:
1) Providing direct technical support to customers in presale stage to persuade customers to adopt Cadence Design IP solutions for their applications
2) Interface with customer architects and Design IP business unit to enable evaluation of application specific IP performance and features per customer’s SOC requirements.
2) Working with the sales team to manage the IP activities in the region to achieve a high customer satisfaction rate and for building strong customer relationships
3) Providing customer feedback on new/existing requirements for Design IP usage from customers to the IP business unit.
4) Providing direct technical customer support and assistance to enable customers to successfully integrate/use Design IP in their SOC.
5) Writing application notes in situation to facilitate customer usage of the IP

Position Requirements :
1)  Experience in digital/analog design and implementation of controllers/phy
2)  Knowledge of serdes and backend implementation is a plus
3)  Experience with SOC architecture include on-chip fabric (AMBA/Sonics OCP/Arteris NOC), external interconnect protocols (e.g PCIe/Ethernet) and DRAM memory protocols (DDRn, LPDDRn), DRAM PHYs, .NAND Flash (Async, ONFI, Toggle NAND), eMMC/SD, MIPI
4)  Knowing serdes/analog IP is a plus
5)  Exposure to IP-based SOC design flow and real tape-out experience.
6)  Good written and verbal communication skills and problem solving skills are required.
7)  Ability to conduct technical meetings, presentations, seminars and training to customers and to the sales team
8)  Travel within AP region may be required.
9)  Good understanding of the semiconductor IP marketplace and ecosystem is a plus.

globe0968 · 發表於 2014-2-14 14:04:05

Principle SI/PI Engineer
公    司：One world top EDA company
工作地点：上海

Position Description:
Complete power-delivery system analyses across chips, packages and boards. System-level SI analysis, including simultaneous switching noise analysis of high-speed signal transmissions, and advances physical design for single- and multi-chip packages, states-of-the-art 3D packages, and systems in packaged (SiP). The engineer should be able to act as a strong team member and contributor.

Specific duties include:
- Be responsible for building SI/PI/SiP design flow for High-speed IP Design
- Proficiency in Cadence tools: Allegro and Sigrity
- Proficiency in Hspice or spectre simulation, especially in high-speed simulation.
- Good knowledge in modeling, for example IBIS.
- Good knowledge in high-speed PCB design.
- At least eight years experience focus on SiP and SI/PI analysis, excellent communication skills and the uncanny ability to both lead and contribute in a cooperative team environment is required.

Position requirements:
Essential Qualifications:
1. Must have BS degree with 10+ years of applicable experience, MS degree with 7+ years of applicable experience in electrical engineering, microelectronics, comparable engineering science or solid state physics.
2. Essential that the individual demonstrates strong communication, verbal and written. Requires good communication skills in English.

Desirable Qualifications:
A  minimum of seven years relevant experience in industry.
- At least five years experience driving SiP/PI/SI project.
- Will have demonstrated successful completion of 10+ projects as an individual contributor

ranica · 發表於 2014-1-23 08:55:39

Senior/Staff DFT Design Engineer
公    司：A famous IC company
工作地点：上海

Description:
- Block, IP and SoC level DFT implementation (bscan, scan, mbist, jtab, analog test structure, etc.)
- work with IP vendor (internal/external) to analyze DFT integation issues
- DFT STA, constraint generation, formal and timing closure
- DFT flow development and maintenance
- test vectors generation and verification
- interface to backend team on physical design and timing closure
- interface to test engineers on ATE and vectors bring-up and debug
- chip DFT quality sign-off

Qualifications:
Must have:
- minimum 4+/8+ years of DFT design and integration experience
- hands on DFT implementation experience (bscan, mbist, scan, IP testablity integration, at-speed
scan, IDDQ test, ATPG and fault simulation)
- expertise with DFT tools from Synopsy, Mentor, Syntest and Logic Vision
- strong logic design and verification backgroud solid experience in STA
- proficient in Perl, tcl and shell programming
- BSEE degree or above
- good team work spirit

Nice to have:
- familiar with DTV/STB architecture, design, and IP
- proficient in C++ and system verilog

ranica · 發表於 2013-12-12 09:13:17

Principal AMS Physical design engineer
公    司：One world top EDA company
工作地点：上海

职位描述
Skillful capable of physical design of Analog and mixed signal area: Matching sense from transistor, Resistor and capacitor, Power and Ground coupling, Signal path from Differential pairs, etc, if knowledge on digital blocks P&R prefered.
In-depth knowledge and hands-on experience on AMS CAD support, such as write Scrips to support PDK(pcell, call back), ams back-end stuffs, including Skill language, Perl, verification runset improvement etc
Proficient with xx layout tools specifically Virtuoso XL and Assura (xx 6.1 experience a plus)
Experience in 65 nm and below analog CMOS layout, verification (DRC, LVS), and top integrated tapeout to foundry
Ability to coordinate with the other analog IC circuit layout,  ensuring robust, efficient, consistent and successful delivery of analog IC circuit layout.
Fundamental understanding of IC design technology and process/methodology
Skilled in Analog IC top level chip assembly including floorplanning and block layout
edicated experience on key macros is prefered: SerDes, High speed/high resolution Data Converters; High Speed PLL''s; Low Noise Design;
Hands-on experience conducting DRC/LVS analysis and recommending appropriate solutions
Solid understanding of IC design technology and process/methodology in AMS layout

Position Requirements:
BSEE degree with >6+ years of applicable experience in advanced analog and mixed signal design industry. Essential that the individual demonstrates strong communication, verbal and written, and project management skills. Requires very good communication skills in English and Chinese.

Company Info Type:
Global Default

Company Information:
xx is the global leader in software, hardware, and silicon IPs that is driving the transformation of the electronic design automation (EDA) industry. This application-driven approach for creating, integrating, and optimizing designs helps customers realize Analog & Digital ICs , System-On-Chip devices, IP and complete systems at lower costs and with higher quality.

ranica · 發表於 2013-8-29 10:01:05

CAD Engineer [系统编号：79171319589]

公    司：semiconductor company
工作地点：北京

Job Description:
Collaborate with *** CAD teams to develop industry leading design flows and methodologies for analog and mixed-signal designs using nanometer technologies, with emphasis on improvement of layout productivity of analog circuits, including usage of advanced Cadence IC6.1 features, design for manufacturing (DFM), metal fill, physical verification and tapeout flows. Write scripts and utilities to enhance these design flows. Provide CAD support and methodology training to *** design and layout community. Write application notes and document ***’s analog/mixed-signal CAD flows. Work with EDA vendors to drive ***’s interest with regard to analog/mixed-signal tools.

Qualifications:
-       BSEE or above, with 3~5 years relevant industry experience.
-       Solid understanding of advanced semiconductor process technologies
-       In depth familiarity with layout of analog and mixed signal circuits including knowledge of layout effects (i.e. matching, reliability etc.) and DFM rules for advanced technology nodes
-       Understanding of nanometer design rules and physical verification runsets
-       Solid knowledge of Cadence DFII
-       Knowledge of physical verification tools like Mentor Graphics’ Calibre
-       Knowledge of Skill, perl or other programming languages
-       Strong written and verbal communication skills

ranica · 發表於 2013-7-23 14:14:51

CAD Engineer

公    司：IC设计公司
工作地点：深圳

Responsibilities:
1) Provide support and trouble-shooting to designers for EDA tools.
2) Help to construct customed in-house analog and layout design flow
3) Maintain and 修改 EDA tools for analog and layout design.
4) Help designers to use new features in EDA tools, or new EDA tools.
5)Maintenance of PDK and all design librarise

Requirements:
1) At least 2 years of CAD or IC design relative work experience.
2) Capable of using C language, Cadence Skill language and Perl.
3) Familiar with EDA tools including Hsim/Hspice/Spectre, Virtuoso and Calibre.
4) Familiar with analog and layout design flow.
5) Familiar with SOC design flow is a plus.
6) Experience of circuit design or layout design is a plus.

ranica · 發表於 2013-7-2 10:08:17

Staff/Senior CAD
公    司：A famous IC company
工作地点：上海

Job Duties:
The candidate will collaborate with Sunnyvale CAD team to support Shanghai design center.
1)       Industry leading edge ASIC design flow and methodology development
2)       Design tools/script development to improve design automation and productivity
3)       EDA tools evaluation, license set up and upgrade
4)       Work with EDA vendors to solve design flow or tool issues
5)       Design database management and maintenance
6)       Local engineers working environment support and Linux/Unix servers/system support

Qualifications:
-          Experience on CAD support for digital/analog/mixed-signal IC design
-          Familiar with IC design flow related EDA tools (Synopsys, Cadence Mentor, etc.) setup under Linux environment
-          Working experience in license set up for EDA tools, version control tools and bug trace tools
-          Excellent script languages skills for internal tool development, such as Perl, Tcl, Shell, Skill and Python
-          Experience in Pcell development is a plus
-          Customer oriented, good communication skill
-          B.S. Degree or above in Electrical Engineering or Computer Science. Major in Microelectronics is a plus.
-          At least 3-5 years CAD experience in IC design company
-          English language skill in writing and speaking.

ranica · 發表於 2013-6-13 10:59:20

Lead Implementation Services Engineer（Shanghai）

公    司：NO.73-One world top EDA company
工作地点：上海

职位描述
1.Ability to handle large sized design implementation tasks & architectural tasks alone.
2.Ability to assess Customer''s Design environment, to understand his application needs & to build new Design environment based on specifications & available Cadence tool technology.
3.Ability to acquire a basic understanding of the (services) business environment of Cadence within 1 month.
4.Working on multi person projects of varying complexity, working especially in a multi-site/multi-cultural project. The latter requires good communication skills in English.
5.Feeling responsible for technical delivery as well as business development & opportunity creation. Behavioral competencies: Teamwork; Customer focus; 6.Accountability; Communication; Coaching & feedback; Employee development; Leadership.

职位要求
1.BS degree with 10+ years of applicable experience, MS degree with 7+ years of applicable experience in electrical engineering, microelectronics.
2.Essential that the individual demonstrates strong communication, verbal and written, and project management skills.
3.Requires good communication skills in English.

ranica · 發表於 2013-6-7 17:32:41

CAD Engineer

公    司：NO.25-A famous IC company
工作地点：上海

Job Description:
Provide first-class system administration services to engineering community
Install software, apply patches, manage file systems, monitor performance and troubleshoot users’ login
environment.
Perform system failure analysis and recovery to insure consistency and integrity of file systems.
Set up and configure hardware and software for user workstations as well as enterprise servers.
Automate administrative tasks via scripts and cron jobs
Liaison with vendors and support evaluating product procurement.
Support main stream EDA tools’ user interface

Job Requirements:
BS degree in Computer related field
3+ years of relevant experience
Hands on experience with scripting and NIX operating system
Proficient with CAD system administration tasks
Knowledge of X-windows programs (VNC, Exceed, ..) and file-sharing utilities (SAMBA, ftp, ..)
Excellent written and verbal communication skills
Fluent in English
Self-motivated, team oriented and professional ethic

ranica · 發表於 2013-5-24 13:41:58

CAD Engineer
公司：NO.25-A famous IC company
工作地点：上海

Job Description:
Provide first-class system administration services to engineering community
Install software, apply patches, manage file systems, monitor performance and troubleshoot users’ login
environment.
Perform system failure analysis and recovery to insure consistency and integrity of file systems.
Set up and configure hardware and software for user workstations as well as enterprise servers.
Automate administrative tasks via scripts and cron jobs
Liaison with vendors and support evaluating product procurement.
Support main stream EDA tools’ user interface

Job Requirements:
BS degree in Computer related field
3+ years of relevant experience
Hands on experience with scripting and NIX operating system
Proficient with CAD system administration tasks
Knowledge of X-windows programs (VNC, Exceed, ..) and file-sharing utilities (SAMBA, ftp, ..)
Excellent written and verbal communication skills
Fluent in English
Self-motivated, team oriented and professional ethic

ranica · 發表於 2013-5-23 16:03:35

Staff PnR/CAD Engineer
公司：NO.82-A famous IC company
工作地点：上海

Responsibilities
1. IC Place and Route for designs up to a few million gates in deep sub micron technology, with advanced low power flow; Timing, Power, IR drop and Noise analysis
2. DRC/LVS command file, rule deck and chip tape-out handling and support;
3. IC-CAD tool and design flow support

Mandatory Skills
1. Place and Route in deep sub micron technology; timing, power, IR drop and noise analysis
2. In depth understanding of IC layout and command files, IC process flow
3. Good knowledge of Linux/Unix and ICCAD tools
4. Good knowledge of digital and analog IC design flow
5. Scripting language and file/database conversion techniques
6. Fluent in English

Preferred Skills
1. IC hand-crafting layout design
2. VLSI design and verification
3. Library design and characterization

Education
University Degree of Microelectronics, Electrical Engineering or Computer Science,
Master degree preferred

Experience
8+ years of working experience, 2+ experience in US or Europe based ICCompany.
3+ years of experience in Place and Route
3+ years of experience in IC-CAD, CAE or tape-out handling

ranica · 發表於 2013-5-15 15:45:30

电路设计工程师
客户 High
地点 Beijing

工作职责与具体内容：
负责模拟/定制电路模块的设计，包括电路设计，仿真，版图规划和布局并指导版图设计，提供模型，流片回来的测试等。

职位技能要求
·熟练使用主要的EDA工具，如virtuoso,hspice,hsim,spectre等；
·有以下IP（其中之一）设计经验并成功留片：PLL，高速IO，ADC，电源管理模块，SRAM；
·良好的中英文交流及文档书写能力
·具有良好的分析问题，解决问题能力及团队合作意识；

工作经验
2年以上工作经验, 具有扎实的CMOS基础知识

学历/专业
E.E硕士学历

ranica · 發表於 2013-5-15 15:44:03

CAD Engineer
客户 IC设计公司
地点 Shenzhen

Responsibilities:
1) Provide support and trouble-shooting to designers for EDA tools.
2) Help to construct customed in-house analog and layout design flow
3) Maintain and update EDA tools for analog and layout design.
4) Help designers to use new features in EDA tools, or new EDA tools.
5)Maintenance of PDK and all design librarise

Requirements:
1) At least 2 years of CAD or IC design relative work experience.
2) Capable of using C language, Cadence Skill language and Perl.
3) Familiar with EDA tools including Hsim/Hspice/Spectre, Virtuoso and Calibre.
4) Familiar with analog and layout design flow.
5) Familiar with SOC design flow is a plus.
6) Experience of circuit design or layout design is a plus.

ritaliu0604 · 發表於 2013-4-24 14:02:18

客户 IC设计公司
地点 Shenzhen

职位描述 Responsibilities:
1) Provide support and trouble-shooting to designers for EDA tools.
2) Help to construct customed in-house analog and layout design flow
3) Maintain and update EDA tools for analog and layout design.
4) Help designers to use new features in EDA tools, or new EDA tools.
5)Maintenance of PDK and all design librarise

职位要求 Requirements:
1) At least 2 years of CAD or IC design relative work experience.
2) Capable of using C language, Cadence Skill language and Perl.
3) Familiar with EDA tools including Hsim/Hspice/Spectre, Virtuoso and Calibre.
4) Familiar with analog and layout design flow.
5) Familiar with SOC design flow is a plus.
6) Experience of circuit design or layout design is a plus.

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yhchang · 發表於 2008-2-13 23:11:08

主要是要克服高層的腦袋所思維不合理的 Tapeout Deadline吧
一個新製程居然壓 3個月做出來
真是虧董事長想得出來
3個月後連LAYOUT都還沒開始動工
最後一共DELAY了半年

tommywgt · 發表於 2007-3-9 18:47:55

回到原本話題...
身為IC設計者，我面對的最大壓力？

應該是回家面對老婆或者是女朋友(要加個s嗎?說不定老婆也要加個s

)吧....哈...我來搞笑,

jimy · 發表於 2007-3-9 13:18:39

那家會不會是創X啊?
pupu 土法煉鋼

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身為IC設計者，我面對的最大壓力？

CAD Engineer

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