|
大家好 我想請問一個問題,我將兩個書上的範例結合在一起想寫成一個0加到9的VHDL程式,
& g6 X5 }8 C* t4 A9 H2 i但現在出現了一個問題,當我程式加上FREE_COUNTER這個block執行模擬時這個block內, h4 M1 Y) C* ` N( y4 ~
的 DIN <= Q(23 downto 20); 的輸出值卻一直是"0000",變成4 s6 o8 }1 w/ v) _4 A
我只能用cnt的值來控制我的七段顯示器輸出了,我想請問大家可能是什麼出了問題?
4 V. Z( S- ]% O# Y4 G* X4 Q
, B2 z* ?( h M' }7 F" i+ D( p另外我想再請問一個問題,我將我模擬的波形放在附件中,seg_output的輸出會有一段一段5 P3 I# h8 F" h: t' e2 D
很不規則的訊號該怎麼消除呢?
' d( \8 \: o8 w F
5 p- ]# Z$ W7 `- q- Z1 S" p, M: s0 d# q不好意思耽誤各位的時間,麻煩大家了!!
- s/ s6 E) m# s. W! p% B6 x) }' x
**字數太多了,我把宣告省略了**
7 Y; d2 I# e- \8 y" kbegin
: B6 M) h- n" J4 v* A" CSYSTEM_CONNECT : block
: s1 p; c' o) J- Wbegin# J0 x! j3 H/ f9 s) a& |
seg_output(6 downto 0) <= seg;
9 w; i, F4 }8 N$ { e0 a, k seg_set <= seg_s;
5 N4 X( d1 K. n; aend block SYSTEM_CONNECT;
; n7 T: F( f& D( k$ n
; K8 x7 `' t) x2 r$ jSYSTEM_SET : block5 h1 q" S0 D- X) o) j& V% j c+ W. g2 c
begin, S+ A9 X4 x/ r0 A8 s
process(CLK). L4 I+ E7 ?8 ~; K _& }
VARIABLE cnt : std_logic_vector(3 downto 0);
& l& O, W8 I5 n begin
- s+ N6 b2 P9 H if CLK'event and CLK = '1' then j5 J2 \, r) o- k e8 E' [! Q5 m
if clrn = '0' then
" T* m2 `& n# g. p: K7 w$ K0 ? cnt := "0000";
& S/ a0 ~1 z- j8 [, @0 F elsif load = '0' then1 t* e7 O9 q( G# e ]; C
cnt := D ;. i8 r" w6 m' H
elsif (ENP and ENT) = '1' then _6 N [) B. r3 i$ i
if cnt = "1001" then
/ Z) k) i$ |3 Y7 O: h! A+ j cnt := "0000" ;
9 D$ `7 w8 e: E- e5 O7 A' u else0 v( b+ w3 |; V1 W' b6 T
cnt := cnt + 1;
) d- X" _# Y8 A7 F6 \ end if ;
: h! J3 H0 R E2 y end if;8 Z. F2 F0 R" I
end if ;- z+ \8 `+ a. ~$ s- R
display <= cnt;* J' O0 x9 g& c- Y/ k* @" d
--DIN <= cnt;
0 u" b7 O& ^. `% B Co <= cnt(3) and cnt(0) and ENT;
7 Y! q2 `7 g2 P+ ?; r$ P9 d7 l7 } end process;% M* ]# v- f V1 a; t) x8 m( v: x
end block SYSTEM_SET;
$ g$ \9 @4 V' n9 i, o0 @, S" v! z: _: i9 l+ J
FREE_COUNTER : block
/ F( c% y$ z5 H- ~7 {6 [& z signal Q : STD_LOGIC_VECTOR (23 downto 0);
: E/ d% `8 O, T% k, D5 V3 k9 q signal D_FREEC : STD_LOGIC_VECTOR ( 1 downto 0);
) Q9 r8 N3 B7 |" m+ D* Z* w! B. e. c1 ]; [' i
begin
?5 C2 L2 I, H h process (CLK)
) I% @* L; ~: A% X7 v begin
# D: f1 i: J" o0 j8 r& l: O if CLK'event and CLK= '1' then, r1 t" g; h0 P3 ~2 T+ P, Z& i4 f
Q <= Q + 1 ;
! I8 s f+ w' U end if ;* H* x7 T# X$ _4 i! }/ K+ M
end process;* N) m* A$ ?# y# F
DIN <= Q(23 downto 20);. l7 g6 o( t4 y0 A) n+ n6 a7 k U
D_FREEC <= Q(15 downto 14);+ d' V6 g4 S7 _. |# k
seg_s <= "0001" when D_FREEC=0 else
8 h1 _& l1 n8 P "0010" when D_FREEC=1 else
3 ?) c$ b; P# W "0100" when D_FREEC=2 else
; v# B0 A/ N5 Y2 s, J2 r "1000" when D_FREEC=3 else
) j' ?. Q0 H6 _; ? "0000"; I% |1 n" ?6 y
end block FREE_COUNTER;2 p; [! _$ V$ n% t% L0 C, }
SEVEN_SEGMENT : block
( Z0 L) v! F9 {! ubegin
& N+ O) c' v1 X7 h$ E& P- e/ ~
" B. O" J4 q0 P4 U8 k- eseg <= "0111111" when DIN = "0000" else3 l7 `" z" z* |
"0000110" when DIN = "0001" else
2 ^* q: s: M) C( N2 _ "1011011" when DIN = "0010" else
* `" L# S$ e& R" Y' K s 省略
- N1 @3 N) |3 E "1110111" ;% n0 v. S5 H1 G+ |: O1 S
8 |" Y3 g/ K( n3 ~/ }
end block SEVEN_SEGMENT;
% n0 Q: Y2 ^* P9 Kend zeroto_9_type2_arch; |
本帖子中包含更多資源
您需要 登錄 才可以下載或查看,沒有帳號?申請會員
x
|