想請問一下,為什麼我ㄧ邊丟資料,等FIFO滿旗標後,另一邊再去讀,都會掉資料,我的系統是8MHZ與20MHZ的,使用FIFO是IDT的7203L50,有人碰過這樣的問題嗎,要怎嚜解決, 8 |" k [, O. e7 c' u比起硬體的FIFO,我是否要更換FPGA來做FIFO,才不會碰到這樣的問題???
for fast system read slow , no problem, % m! l/ e2 a) ]2 Y4 |. j/ E8 n1 r9 E. F' _. k
For low system read fast...may have problem... 8 O4 Y3 H L/ R! v" ]/ Q1 VUse half full or near fulll (it can design by fifo)