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//some example
; [% A$ H) F1 E6 w& \) r8 o6 s7 X. o9 q0 k! i+ g
// define variable
, N5 \2 \- K/ Y) d( H( f% iVARIABLE RVM1 0.077 // Metal-1 resistor 8 n, G' F: }7 `4 t7 r) ?8 b9 b0 m
VARIABLE RVM2 0.055 // Metal-2 resistor; z. M. C3 ?' w# s
VARIABLE RVM3 0.055 // Metal-3 resistor# B: r' S; i. K; Y9 j
% K \: c+ ~) Q' u3 Y' O" ]
// lvs option4 h2 r7 y/ R0 C! e" d8 u
LVS SPICE PREFER PINS YES* U' B; u& g% k$ }: ]( e
LVS ABORT ON SUPPLY ERROR NO+ e0 z3 Q% H: y: |3 ], [; m: F
LVS ALL CAPACITOR PINS SWAPPABLE YES
: I. ^& I+ {$ f& m+ HLVS RECOGNIZE GATES NONE- v* |# G, B( Y U$ |0 ~
LVS IGNORE PORTS NO! |& O8 N$ t9 q! f t
LVS CHECK PORT NAMES YES& E3 N+ o1 G8 K! }" ~
LVS REDUCE PARALLEL BIPOLAR YES
: j" u6 [: Y4 w) {: |LVS REDUCE PARALLEL MOS YES
: g& p# s( ^) [( S( nLVS REDUCE PARALLEL DIODES YES* l+ s) H0 X6 t2 J7 p4 U( x
LVS REDUCE PARALLEL CAPACITORS YES
- N; j, O; @% A0 o& `LVS REDUCE PARALLEL RESISTORS YES
" L* X* M9 |3 {. Q, ~LVS REDUCE SERIES RESISTORS YES //Smashes series resistors5 ]: Q8 n1 _& f4 p5 @
LVS REDUCE SERIES CAPACITORS YES //Smashes series capacitors4 p; y% s6 W! R# \
LVS REDUCE SPLIT GATES NO //Smashes MOS split-gates.: O/ u5 D7 Q m9 I/ ]
//LVS FILTER UNUSED OPTION B D E O) i7 ~: {6 \0 U: F
LVS FILTER UNUSED OPTION AB RC RE RG
; @. n7 ~+ A4 W2 U7 NLVS PROPERTY RESOLUTION MAXIMUM 65536 // ALL
, ~7 ~' t8 ^; O7 p
( w5 A* ]/ d3 } u' ]// layer definition O y0 D; Q3 \' l; _) _$ A! ?/ z
LAYER DNW 1 // DNW -- Deep N-Well' I0 ^, ~0 T8 n' C) B4 ~
LAYER NTN 11 // Native Device Blocked Implant+ p s* Q- n; T+ q/ Y2 F- d5 [3 S
LAYER NWELL 3 // NW -- N-Well: ^: _5 u1 P% Z5 ~( `3 B- v( L# u9 @1 G4 i
LAYER OD 8 6 7 // OD -- Thin Oxide2 V+ n( ^9 v7 w5 X/ c3 m
% b+ ?5 f/ m* n# y// layer operation. E% O: Y2 V- `# h
rpolywo1 = POLYG AND RHDMY ! C0 y; p: G, g$ G9 S" h4 r
rpolywo2 = rpolywo1 AND RPO
+ C7 K' b0 c( E) ~! A. [. U' Rdiff = OD NOT RODMY
: i, b# G( ?. [( q+ m: T+ trp1 = RPDMY NOT INTERACT diff
9 T& H3 N& _; O: X x1 u1 ~7 Np1rdum = rp1 INTERACT POLYG
; a& M5 N! S) v' e8 I! t
- X# L. X" T) V8 L// connect statement) P B" S" W* J- o. A- ?, w! T
CONNECT metal1 c2poly BY pl2co
- L- A0 C x" h6 |! bCONNECT metal1 tndiff BY pl1co
! e l: T. `, m5 L8 RCONNECT metal1 poly BY pl1co
- h1 u' `4 i' X5 oCONNECT metal1 tpdiff BY pl1co9 L; X9 ^* t! x$ s9 ?/ o
CONNECT metal2 metal1 BY VIA1( l4 U4 T- y6 j3 @0 O5 F) o
CONNECT metal3 metal2 BY VIA2
1 |3 o; q2 E& W8 LCONNECT metal4 metal3 BY VIA3
1 Z' B9 `( t, \* ~" G, c) zCONNECT metal5 metal4 BY VIA4* P! q7 r) F% ~5 @- D# @ ]
CONNECT metal6 metal5 BY VIA5 o5 m) s0 s% U9 q) U- X
CONNECT metal7 metal6 BY VIA6 G% ^ [# D' Z5 K
CONNECT metal8 metal7 BY VIA78 B' F5 N+ [: F; |
CONNECT metal8 CTM_M7 BY CV7
3 B! V$ }# i& I1 }4 \2 z9 C) @1 y; e9 l# H8 a
// device definition
: h6 q; D: o5 ~' M* y9 q) aDEVICE MN(nmos) nmos poly(G) ndiff(S) ndiff(D) psub(B) [! I* _: i& a. T$ B3 R
property W,L. J" w6 }8 D4 h1 Z, o- J
W=(perimeter_coincide(nmos, ndiff ) + perimeter_inside(nmos, ndiff)) / 2
9 _* @4 L0 L7 G" l7 F L=area(nmos) / W
/ z& T, m& ?! Y1 s! H# v]2 x. o& Z# h" f) ]
2 k {3 v+ S0 H2 }% ^4 u1 f
// trace property
1 h9 \5 M' ?8 C" {& CTRACE PROPERTY MN(nmos) L L 0
?. `3 W7 P5 E" HTRACE PROPERTY MN(nmos) W W 0 |
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