MIPS Unveils Industry's First Multi-threaded, Multiprocessor IP Core

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MIPS Technologies Unveils Industry's First Multi-threaded, Multiprocessor IP Core for the Embedded Market
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MIPS32(R) 1004K(TM) Coherent Processing System Offers Superior Performance through Multi-threading
( g  `8 ]; z$ p+ ~- aMOUNTAIN VIEW, Calif., April 1, 2008 /PRNewswire-FirstCall/ -- MIPS Technologies, Inc. (NASDAQ: MIPS), a leading provider of industry-standard architectures, processors and analog IP for digital consumer, home networking, wireless, communications and business applications, today introduced the MIPS32(R) 1004K(TM) coherent processing system-the industry's first embedded multi-threaded, multi-processor licensable IP core. The new multi-core offering provides among the best performance efficiency and configurability in a multi-processing system -- up to four single- or multi-threaded processors integrated with advanced system coherency. MIPS Technologies' multi-core debut marks yet another performance milestone for the company, following last year's launch of the high-performance MIPS32(R) 74K(TM) core-the industry's first single-threaded processor core to achieve frequencies greater than 1GHz.
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"There is growing demand for processor performance in embedded applications," said Christian Heidarson, principal analyst for the semiconductor group of technology advisory firm Gartner. "Traditional frequency scaling is limited by power constraints, so additional performance must be achieved through parallelism. For highest efficiency, combining multi- threading and coherent multi-core has great potential."
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Unlike other embedded IP offerings, MIPS Technologies has a unique performance advantage inherent in its single core processors. MIPS has optimized single core performance by maximizing single pipeline efficiency via multi-threading in the MIPS32(R) 34K(TM) core, as well as achieving increased processor headroom and generating 1GHz+ frequencies with a superscalar, out- of-order pipeline in its 74K(TM) core. For many high-volume embedded applications, the need for significantly higher performance levels is now driving a move to coherent multi-core implementations that minimize system resources and maximize SoC performance on mainstream silicon processes and clock speeds. The 1004K(TM) core optimizes CPU performance on a shared memory system, enabling multiple functions and applications to be implemented in a single product-all running concurrently and responsively under symmetric multiprocessing (SMP)-based operating systems.
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) s8 J0 N2 m+ X( ^# [; ]- f( G"With our multi-core solution, MIPS Technologies offers designers two paths to higher performance for next-generation embedded applications -- the 74K core for the fastest, single-threaded application, or the 1004K core for coherent multiprocessing scalable to even higher levels of performance," said John Derrick, president and general manager of the Processor Business Group, MIPS Technologies. "MIPS Technologies is now uniquely positioned to offer customers a multi-threaded coherent multiprocessing solution, the industry's highest performance cores with advanced cache coherency and multiprocessing support, and one of the richest ecosystems for products in the digital living room and beyond."
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The 1004K coherent processing system helps lower SoC development costs, since for many applications, fewer processors are needed than with other multi-processor solutions. Multi-threading in each CPU provides significant performance gains over single-threaded multiprocessor offerings. A wide array of key vertical applications, including digital home entertainment, home networking and office automation, are strongly poised to benefit from coherent multi-processing using multi-threading. In addition, the 1004K core offers a broad array of options for increased design flexibility. Designers can add CPUs to scale performance for their specific application requirements. The multi-core Coherence Manager (CM), the foundation block for intelligent system coherency, is configurable for one to four single- or multi-threaded cores with an I/O Coherence Unit (IOCU) that provides optional hardware coherence for I/O peripherals to remove the overhead of implementing this function in software.
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Additionally, the 1004K core provides a highly scalable performance migration path for the popular MIPS32(R) 24K(R) and 34K(TM) core families. Since the 1004K core is MIPS32-compliant, designers can leverage an extensive base of existing software. Two initial versions of the 1004K core family will be available this quarter: the MIPS32 1004Kc(TM), which provides a coherent processing system using base integer cores, and the MIPS32 1004Kf(TM), which uses integer cores plus floating point units.
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4 H; }5 ^' B, L/ b# d+ _MIPS Technologies provides the number one processor architecture across a wide array of high-growth markets, including digital television, broadband access, WiFi, cable set-top boxes, DVD recorders, HD DVDs, and VoIP. The company offers the most comprehensive line of processor cores available for the embedded market-ranging from high-performance to low power products with unique efficiencies and cost advantages for next-generation SoC designs. MIPS Technologies licenses its intellectual property to leading semiconductor companies, ASIC developers and system OEMs. As an industry-standard architecture for more than two decades, MIPS Technologies provides the most extensive range of scalable microprocessors in standard, custom, semi-custom and application-specific products worldwide. The MIPS(R) Ecosystem provides a robust infrastructure of world-class standard tools, software suites and services to help ensure rapid, reliable, high-quality and cost-effective SoC development.

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2008/7/22- 美普思(MIPS)宣布CodeSourcery已推出針對其最佳化的Sourcery G++版本，該套件是以GNU Toolchain與Eclipse IDE為基礎的完整C/C++開發環境。該版本支援所有美普思核心，包括MIPS32 24K核心與超純量(Superscalar)MIPS32 74K核心的效能提升，以及其他最佳化措施。同時亦加入支援Linux應用程式的絕對定址碼(Non-position Independent Code)能力，有效提升Linux系統效能。  

Sourcery G++ for MIPS是以GNU Toolchain為基礎的完整軟體開發環境，其中包括GNU C/C++編譯程式、GNU組譯程式與連結程式、執行階段函式庫(Runtime Libraries)、原始程式碼與組合語言層級除錯程式、支援微處理器除錯介面(Microprocessor Debug Interface)以連接MIPS System Navigator Probes與MIPSsim模擬系統，以及以Eclipse為基礎的整合式開發介面(IDE)選購項目。Sourcery G++可在Windows與Linux主機上執行，支援非即時作業系統(Bare-iron)程式，以及針對GNU/Linux開發的簡易版(Lite)、個人版(Personal)與專業版(Professional)，專業版客戶可擁有CodeSourcery的無限制支援。  

美普思處理器事業群行銷副總裁Jack Browne表示，很高興能與CodeSourcery合作，提供以GNU為基礎的Toolchain最佳化新版本。美普思致力於提供客戶最佳工具，協助其達成目標，此次在Sourcery G++上的努力就是最好證明。美普思將持續與CodeSourcery合作進行Toolchain最佳化，最終目標是將CodeSourcry技術整合到美普思銷售和支援的產品中。