靜電放電測試

wesleysungisme

For ESD test (HBM)
+ @  }# o. T$ e: kThe following are the test combination:
1. Power to Power
* T) e  h! D% q6 K* F; v' ]2. Power to Ground
* o8 G( ?1 |. x* O4 u. Z3. IO to Power
4. Io to Ground
5. IO to IO
- W1 }2 ?& R( g# ?# k9 `4 p(different power domain need to be treated as different power. For ground usually you can treat as one group_silicon use substrate as common ground. But if you measure two different ground pin/ball > 2ohms. It should be seperated as 2 grond.)

the total zap time fomula will be~ 2(+/- polarity) X (IO#X(P#+G#)+IO#+P#X(P#-1)X(P#-2)X...X1+P#XG)
For example: You have IO1/IO2/IO3/P1/P2/G1
2x((3X(2+1)+3+2X1+2X1)=25(multiple the zap interval)
9 f  \# b6 u& o8 ]2 p" o; Q; L$ w& qSo for high pin count it will take a lot of time. But it won't take more than a week(for one chip).

For your reference.