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LOAD SDC FILE時2 l6 b$ }. L3 L8 M( U$ |: k8 d+ k
Astro 訊息
9 A' @+ B7 U8 f n" N: L---------------------------------------------------------------------------
- h) D0 e' ^' P$ B8 q8 p$ NInfo: starting Tcl processing% Q7 R! Y! r; a3 @2 b( k7 ~
Info: building design object name tables # d2 W2 d8 @2 i
Warning: No pins matched 'TOP/test/mul/A[26]' (SEL-004)2 Q% W. @* A# U) I* z3 Y
Warning: No pins matched 'TOP/test/mul/A[25]' (SEL-004)
, z. l p- u/ O# X" J: e+ [* @; p2 z. l
4 K* a0 f0 g2 |3 p+ [1 Z% T) O----------------------------------------------------------------------------
5 ~0 s# A1 w7 ]( e% I0 G) pSDC FILE' L5 ~( d& C9 }1 ~- K' R9 b
. ?# s, B" I' R5 R+ N# }
set_multicycle_path 9 -through [list [get_pins \4 I; I. e" f0 O2 X4 P& {
{TOP/test/mul/A[26]}] [get_pins \
$ k$ n9 ~# m, R/ [# b{TOP/test/mul/A[25]}] [get_pins \
% T8 E" q0 w o) c
R6 T; G9 @+ Z. Q8 j. `
$ Y- B3 N6 U' `& k# U-----------------------------------------------------------------------------& v1 F6 ?0 P% U$ \
Verilog File: W F) E) o4 j3 P- P& @, _. m
4 W! Z8 Y- ]& N0 a5 [& S uniquify_mul_0 mul ( .A(icwAeYfSum[26:0]), .B(9 j; ?3 k" m' K7 l% O8 k# F3 b
icwAeYfNum[18:0]), .C(ae_avg) ); |
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