FPGA 使用verilog設計一個摩斯密碼解碼器

pk3089684 · 發表於 2021-5-26 17:23:23

我們的程式在Quartus II裡面可以compile
可是當要用VeriInstument來run我們的程式的時候
都會跳出「Parse User Design Failed」的提醒
我們無從得知邏輯錯誤的原因(因為也不會顯示)
想請問各位大大，或許可以提示一下我們的程式上有哪些錯誤的設計嗎? ><

我們的發想是，希望可以利用BUTTON判斷長短音然後把讀到的摩斯碼在lcd上顯示出一個完整的單字。

*-------------------------------------主程式-------------------------------------*

module morse_decoder
   (Clk ,morse_code ,enter ,Reset ,lcd_en ,lcd_db ,lcd_rs ,lcd_rw ,lcd_rst);

input Clk,morse_code,enter,Reset;

output lcd_en,lcd_db,lcd_rs,lcd_rw,lcd_rst;

wire  PbInput;
wire  PbEnd;

assign PbInput = morse_code;
assign PbEnd = enter;

wire [7:0] Letter;
reg  [7:0] VgaLetter;

always @(posedge Strobe)
begin
VgaLetter <= Letter;
end

button_sm buttonsm(.CLK(Clk), .RESET(Reset), .PB(PbInput), .SHORT(Short), .LONG(Long));

alphabet letterdecoder(.RESET(Reset), .Clk(Clk), .LONG(Long), .SHORT(Short), .END_CHAR(PbEnd), .LETTER(Letter), .STROBE(Strobe));

TextLCD(.LETTER(VgaLetter), .ClkPort(Clk), .rst_n(Reset), .lcd_en(lcd_en), .lcd_db(lcd_db), .lcd_rs(lcd_rs), .lcd_rw(lcd_rw), .lcd_rst(lcd_rst) );

endmodule

pk3089684 · 發表於 2021-5-26 17:24:30

*-------------------------------------button_sm buttonsm-------------------------------------*

`timescale 1ns / 1ps

module button_sm(input CLK, input RESET, input PB, output SHORT, output LONG
);

reg [5:0] state;
reg [27:0] counter;
reg [0:0] short_reg;
reg [0:0] long_reg;

assign SHORT = short_reg;
assign LONG = long_reg;

localparam
INI = 6'b000001,
WAIT = 6'b000010,
BP = 6'b000100,
SHORT_STATE = 6'b001000,
LONGWAIT = 6'b010000,
LONG_STATE = 6'b100000;

always @(posedge CLK, posedge RESET)
begin
if(RESET)
begin
state <= INI;
short_reg <= 1'b0;
long_reg <= 1'b0;
counter <= 28'b0000000000000000000000000000;
end
else
begin
case (state)
INI: begin
//RTL
short_reg <= 1'b0;
long_reg <= 1'b0;
counter <= 28'b0000000000000000000000000000;

//NSL
if(PB)
begin
state <= WAIT;
end
end

WAIT: begin
//RTL
counter <= counter + 1;

//NSL
if(!PB)
begin
state <= INI;
end
else if (counter[23])
begin
state <= BP;
end
end

BP: begin
//RTL
counter <= counter + 1;

//NSL
if(PB)
begin
if(counter[25])
begin
state <= LONGWAIT;
end
end
else //if !PB
begin
if(counter[24])
begin
state <= LONG;
end
else
begin
state <= SHORT_STATE;
end
end
end

SHORT_STATE: begin
//RTL
short_reg <= 1'b1;

//NSL
state <= INI;

end

LONGWAIT: begin
//NSL
if(!PB)
     begin
     state <= LONG_STATE;
     end
end

LONG_STATE: begin
//RTL
long_reg <= 1'b1;

//NSL
state <= INI;
end

endcase
end
end

endmodule

pk3089684 · 發表於 2021-5-26 17:25:02

*-------------------------------------alphabet-------------------------------------*

`timescale 1ns / 1ps

module alphabet(
   input RESET,
input Clk,
input LONG,
input SHORT,
   input END_CHAR,
output [7:0] LETTER,
output STROBE
);

reg[4:0] STATE, LETTER_REG;
reg STROBE_REG;

assign LETTER = LETTER_REG;
assign STROBE = STROBE_REG;


localparam
INIT = 'h0,
A = 'h1,
B = 'h2,
C = 'h3,
D = 'h4,
E = 'h5,
F = 'h6,
G = 'h7,
H = 'h8,
I = 'h9,
J = 'hA,
K = 'hB,
L = 'hC,
M = 'hD,
N = 'hE,
O = 'hF,
P = 'h10,
Q = 'h11,
R = 'h12,
S = 'h13,
T = 'h14,
U = 'h15,
V = 'h16,
W = 'h17,
X = 'h18,
Y = 'h19,
Z = 'h1A,
DONE = 'h1B;

always @ (posedge Clk)
begin
if(RESET)
begin
STATE <= INIT;
STROBE_REG <= 1'b0;
LETTER_REG <= 5'b00000;
end
else
begin
case(STATE)
INIT:
begin
STROBE_REG <= 0;
if(SHORT) STATE<=E;
if (LONG) STATE <=T;
end
A:
begin
if(SHORT) STATE<=R;
if (LONG) STATE <=W;
if(END_CHAR) STATE<=DONE;
LETTER_REG <= STATE;
end
B:
begin
if(END_CHAR) STATE<=DONE;
LETTER_REG <= STATE;
end
C:
begin
if(END_CHAR) STATE<=DONE;
LETTER_REG <= STATE;
end
D:
begin
if(SHORT) STATE<=B;
if (LONG) STATE <=X;
if(END_CHAR) STATE<=DONE;
LETTER_REG <= STATE;
end
E:
begin
if(SHORT) STATE<=I;
if (LONG) STATE <=A;
if(END_CHAR) STATE<=DONE;
LETTER_REG <= STATE;
end
F:
begin
if(END_CHAR) STATE<=DONE;
LETTER_REG <= STATE;
end
G:
begin
if(SHORT) STATE<=Z;
if (LONG) STATE <=Q;
if(END_CHAR) STATE<=DONE;
LETTER_REG <= STATE;
end
H:
begin
if(END_CHAR) STATE<=DONE;
LETTER_REG <= STATE;
end
I:
begin
if(SHORT) STATE<=S;
if (LONG) STATE <=U;
if(END_CHAR) STATE<=DONE;
LETTER_REG <= STATE;
end
J:
begin
if(END_CHAR) STATE<=DONE;
LETTER_REG <= STATE;
end
K:
begin
if(SHORT) STATE<=C;
if (LONG) STATE <=Y;
if(END_CHAR) STATE<=DONE;
LETTER_REG <= STATE;
end
L:
begin
if(END_CHAR) STATE<=DONE;
LETTER_REG <= STATE;
end
M:
begin
if(SHORT) STATE<=G;
if (LONG) STATE <=O;
if(END_CHAR) STATE<=DONE;
LETTER_REG <= STATE;
end
N:
begin
if(SHORT) STATE<=D;
if (LONG) STATE <=K;
if(END_CHAR) STATE<=DONE;
LETTER_REG <= STATE;
end
O:
begin
if(END_CHAR) STATE<=DONE;
LETTER_REG <= STATE;
end
P:
begin
if(END_CHAR) STATE<=DONE;
LETTER_REG <= STATE;
end
Q:
begin
if(END_CHAR) STATE<=DONE;
LETTER_REG <= STATE;
end
R:
begin
if(SHORT) STATE<=L;
if(END_CHAR) STATE<=DONE;
LETTER_REG <= STATE;
end
S:
begin
if(SHORT) STATE<=H;
if (LONG) STATE <=V;
if(END_CHAR) STATE<=DONE;
LETTER_REG <= STATE;
end
T:
begin
if(SHORT) STATE<=N;
if (LONG) STATE <=M;
if(END_CHAR) STATE<=DONE;
LETTER_REG <= STATE;
end
U:
begin
if(SHORT) STATE<=F;
if(END_CHAR) STATE<=DONE;
LETTER_REG <= STATE;
end
V:
begin
if(END_CHAR) STATE<=DONE;
LETTER_REG <= STATE;
end
W:
begin
if(SHORT) STATE<=P;
if (LONG) STATE <=J;
if(END_CHAR) STATE<=DONE;
LETTER_REG <= STATE;
end
X:
begin
if(END_CHAR) STATE<=DONE;
LETTER_REG <= STATE;
end
Y:
begin
if(END_CHAR) STATE<=DONE;
LETTER_REG <= STATE;
end
Z:
begin
if(END_CHAR) STATE<=DONE;
LETTER_REG <= STATE;
end
DONE: STROBE_REG <= 1'b1;
default: STATE <= 5'bXXXXX;
endcase
end
end

endmodule

pk3089684 · 發表於 2021-5-26 17:25:19

*-------------------------------------TextLCD-------------------------------------*

module TextLCD(LETTER, ClkPort, rst_n, lcd_en, lcd_db, lcd_rs, lcd_rw, lcd_rst);

input       ClkPort;             // System clock
input       rst_n;             // Asyn. reset, high active
input       LETTER;
output       lcd_en; // LED enable
output       lcd_rs; // register select
                     // 0 : write command register
                     // 1 : write data register
output       lcd_rw; // Read/Write Signal
                     // 0 : write
                     // 1 : No function
output [7:0] lcd_db;
output       lcd_rst;

// ------------
// Local Signal
// ------------
reg [7:0] min_out;
reg  [5:0] sec_out;

// ---------------------
// Main Circuit -- Clock
// ---------------------
// System Clock = 30 MHZ
// msb = 19, 1/60 sec
// testing : msb = 15 ~ 19
// design : 60 sec = 1 min, 60 min = 1 hr.
//parameter msb = 19 ;
parameter msb = 19;
reg  [msb-1:0]  cnt_1;
always @(posedge ClkPort or negedge rst_n)
   if (~rst_n) cnt_1 <= 0;
   else cnt_1 <= cnt_1 + 1;

// ---------------------------------
// Count second (using binary format)
// ---------------------------------
always @(posedge ClkPort or negedge rst_n)
   if (~rst_n) sec_out <= 0;
   else if (&cnt_1) begin
      if (sec_out == 'd59) sec_out <= 0;
      else sec_out <= sec_out + 1;
   end

// ------------------------------
// Count Minute
// ------------------------------
always @(posedge ClkPort or negedge rst_n)
   if (~rst_n) begin
           min_out <= 0;
   end
     else if (&cnt_1) begin
if (sec_out == 'd59) begin
if (min_out[3:0] == 'h59)
min_out[3:0] <= 0;
else
min_out[3:0] <= min_out[3:0] + 1;
end
      end

// --------------------------
// Main Circuit -- TEXT LCD
// --------------------------
wire    lcd_wen1;
reg  [7:0] tmp1;
reg  [7:0] lcd_db;
assign lcd_rs = 1'b1;
assign lcd_rst = ~rst_n;
assign lcd_en = 0;
assign lcd_wen1 = (min_out[3:0] > 'h5) ? 1 : 0;

always @(LETTER)
case(LETTER)
'h0 : tmp1 = 'hxx;
'h1 : tmp1 = 'h41;  // a
'h2 : tmp1 = 'h42;  // b
'h3 : tmp1 = 'h43;  // c
'h4 : tmp1 = 'h44;  // d
'h5 : tmp1 = 'h45;  // e
'h6 : tmp1 = 'h46;  // f
'h7 : tmp1 = 'h47;  // g
'h8 : tmp1 = 'h48;  // h
'h9 : tmp1 = 'h49;  // i
'hA : tmp1 = 'h4A;  // j
'hB : tmp1 = 'h4B;  // k
'hC : tmp1 = 'h4C;  // l
'hD : tmp1 = 'h4D;  // m
'hE : tmp1 = 'h4E;  // n
'hF : tmp1 = 'h4F;  // o
'h10 : tmp1 = 'h50; // p
'h11 : tmp1 = 'h51; // q
'h12 : tmp1 = 'h52; // r
'h13 : tmp1 = 'h53; // s
'h14 : tmp1 = 'h54; // t
'h15 : tmp1 = 'h55; // u
'h16 : tmp1 = 'h56; // v
'h17 : tmp1 = 'h57; // w
'h18 : tmp1 = 'h58; // x
'h19 : tmp1 = 'h59; // y
'h1A : tmp1 = 'h5A; // z
'h1B : tmp1 = 'h00; // space

default : tmp1 = 'h00;
endcase

endmodule

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