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我目前在設計一個pipeline的電路,且有防bubble機制,但在設計的過程中有些問題~1 B7 W( p: N+ ^8 @: C! e5 A
想請問一下大家!!, O* }; H4 N! O7 `
該怎麼設計?, J* l4 e: Z0 R1 D4 h8 @( d
以下是我需要的功能~
- Q' i1 Y6 A' p& \4 C$ y | | | | | | | | | | | | | | | | | | | The next stage data full signal | | | | | | | | | DUT full signal to preceding stage |
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* {& ]& Y$ k0 `! F8 zThereare 5 pipe stages in our pipelining design.
/ A9 M, f' T- s: t: p3 ~It means that the input data can beobserved at the output port after 5 clock cycles. ) F. c) K" f) q
All the stages must be readyto proceed at the same time. ( l2 b# S4 \1 P! X6 z& Y
When d_full is active, you have to keep the outputdata until d_full is disabled. . s1 N) V) I3 G+ B+ Y! Y# P2 e4 J
If d_full is active and all the pipe stages arebusy, you have to generate pp_full to inform the preceding stages to hold data.
3 g+ J3 @: O% W; E% ZThe pipeline bubbles haveto be eliminated when d_full is active.
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