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我目前在設計一個pipeline的電路,且有防bubble機制,但在設計的過程中有些問題~3 e5 g4 T @2 H7 _8 Y
想請問一下大家!!1 {' L% O7 P: L! p0 f* l. }8 b
該怎麼設計?2 A' A3 p/ L) C3 @
以下是我需要的功能~
5 {$ g, n; i8 N# U. X) J6 u) E | | | | | | | | | | | | | | | | | | | The next stage data full signal | | | | | | | | | DUT full signal to preceding stage |
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4 E1 B3 I0 s; ]! RThereare 5 pipe stages in our pipelining design.
9 J5 S5 H( C1 v' Q0 GIt means that the input data can beobserved at the output port after 5 clock cycles.
( Z: o. R4 E1 h5 e* NAll the stages must be readyto proceed at the same time. , S O) q( A1 H, [" v6 G3 d; D$ c3 T- T
When d_full is active, you have to keep the outputdata until d_full is disabled.
- H+ e2 O( B1 g9 iIf d_full is active and all the pipe stages arebusy, you have to generate pp_full to inform the preceding stages to hold data. # Y7 i! D9 h1 v; ]9 i1 C
The pipeline bubbles haveto be eliminated when d_full is active.. @% [4 ?$ h) p, b0 L
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