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我目前在設計一個pipeline的電路,且有防bubble機制,但在設計的過程中有些問題~( q% O: X. u* s) S5 z
想請問一下大家!!
# j- t- z% v5 i$ J/ _8 s該怎麼設計?
9 s6 Z, [: M3 H5 x以下是我需要的功能~7 X9 G5 P, y w. e
| | | | | | | | | | | | | | | | | | | The next stage data full signal | | | | | | | | | DUT full signal to preceding stage |
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Thereare 5 pipe stages in our pipelining design.
8 O% E$ y5 u' N' ^: H; l1 q1 DIt means that the input data can beobserved at the output port after 5 clock cycles. % K/ U5 _1 R; N% [) \
All the stages must be readyto proceed at the same time.
~4 t% h' H. v2 J; Q& SWhen d_full is active, you have to keep the outputdata until d_full is disabled. 6 E8 s i1 S; v; {2 z5 S% F$ n
If d_full is active and all the pipe stages arebusy, you have to generate pp_full to inform the preceding stages to hold data.
; U) E/ ~5 \' x3 n) W. M+ EThe pipeline bubbles haveto be eliminated when d_full is active.! ]& H$ s- U7 G' E
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