Cortex-M0+ IP Core

sinoicboy

7 K4 ]6 R# e  P
' W/ E5 E2 U; a* T4 i! [
( x- P( ^9 r: k( B0 Q
iconstart@gmail.com
) C* G9 o1 S. C! U) Z
                                  AR085-DA-70000-r0p0-03rel0/
. Q5 K! Y4 J* d) V( Q; f# R                                  AR085-DA-70000-r0p0-03rel0/doc/
1 k/ F/ G- e$ ]                                  AR085-DA-70000-r0p0-03rel0/doc/ARMv6-M_architecture/
4af79e0557cc9c6863c2eab0f890aaad  AR085-DA-70000-r0p0-03rel0/doc/ARMv6-M_architecture/DDI0419C_arm_architecture_v6m_reference_manual.pdf
                                  AR085-DC-11001-r0p0-04rel0/
                                  AR085-DC-11001-r0p0-04rel0/doc/
                                  AR085-DC-11001-r0p0-04rel0/doc/errata/
57ce61d69a56fae9dff02a664dc0930a  AR085-DC-11001-r0p0-04rel0/doc/errata/ARMv6-M_Architecture_Errata_List.pdf
                                  AT590-BU-11001-r0p1-00rel0/
b2bb2db05b71fa9e2ecd4c2841c22f3f  AT590-BU-11001-r0p1-00rel0/Cortex-M0+_Product_Errata_Notice_v4.pdf
d305236940b52b92b81e8579435efe7e  AT590-BU-11001-r0p1-00rel0/Cortex-M0+_Software_Developers_Errata_Notice_v4.pdf
2d80706f7a099ac4a9674908c50d730e  AT590-BU-11001-r0p1-00rel0/AT590-BU-11001-r0p1-00rel0.lst
( C7 ~8 ?! K: W; G8 [- Q                                  AT590-BU-50000-r0p1-00rel0/
5 l# R- g+ m0 u9 E/ H; O' ~8 x, |70404309a7929774e3bd8786e10771eb  AT590-BU-50000-r0p1-00rel0/ARM_Cortex-M0+_r0p1-30rel0_ReleaseNote.pdf
! m* f. |6 I+ W" X                                  AT590-BU-50000-r0p1-00rel0/logical/
8 k8 W& n* g9 @* Z, [                                  AT590-BU-50000-r0p1-00rel0/logical/cm0p_dap/
                                  AT590-BU-50000-r0p1-00rel0/logical/cm0p_dap/verilog/
& N3 W* f6 K. U3 y80fe9cfaeb5e260f70aebfcac0bdf888  AT590-BU-50000-r0p1-00rel0/logical/cm0p_dap/verilog/cm0p_dap_dp_cdc.v
& J; `$ X+ P0 [" b$ n) Y063cdb1c994aca1f31971a3d52da426d  AT590-BU-50000-r0p1-00rel0/logical/cm0p_dap/verilog/cm0p_dap_dp_sw_defs.v
17f0e782572ea85e916a26ef804106ac  AT590-BU-50000-r0p1-00rel0/logical/cm0p_dap/verilog/cm0p_dap_dp_jtag_defs.v
db6b0ced453f9ba83035ca0b2d31c55d  AT590-BU-50000-r0p1-00rel0/logical/cm0p_dap/verilog/cm0p_dap_ap_mast.v
+ D: \% q) i, \: K+ Q+ u! z9 I' ~12e85d89d377ef33f7a41f5f49bf20f0  AT590-BU-50000-r0p1-00rel0/logical/cm0p_dap/verilog/cm0p_dap_dp_jtag.v
' j/ u. ]0 }% O1 Y  x% r/ o) Dbb3812a6b967f1ffaa604a858064f1d6  AT590-BU-50000-r0p1-00rel0/logical/cm0p_dap/verilog/cm0p_dap_top.v
' e- F/ V6 s, D2b71a63c5d6843c6a0c64972ca0a3483  AT590-BU-50000-r0p1-00rel0/logical/cm0p_dap/verilog/cm0p_dap_dp.v
fc6a96af9879ce4ccb0c150913d38ab5  AT590-BU-50000-r0p1-00rel0/logical/cm0p_dap/verilog/cm0p_dap_ap_cdc.v
72017024f98163d43c2f77e920560bd3  AT590-BU-50000-r0p1-00rel0/logical/cm0p_dap/verilog/cm0p_dap_ap.v
) b9 X5 L# B0 K; ]- b( m0 M7 j6ca54cbd04210e471b30aaca343e1966  AT590-BU-50000-r0p1-00rel0/logical/cm0p_dap/verilog/cm0p_dap_ap_mast_defs.v
764fcf3fa6ce572a3325f069a591baf6  AT590-BU-50000-r0p1-00rel0/logical/cm0p_dap/verilog/cm0p_dap_dp_pwr.v
+ C' f# R6 |3 k2 `+ `/ \1 x3ffb32cddb6a7e19f9f91e437f7ca59b  AT590-BU-50000-r0p1-00rel0/logical/cm0p_dap/verilog/CM0PDAP.v
75d1d91ab79ae9e0e044ed1ef71cf03e  AT590-BU-50000-r0p1-00rel0/logical/cm0p_dap/verilog/cm0p_dap_dp_sw.v
                                  AT590-BU-50000-r0p1-00rel0/logical/cortexm0plus/
' a# ~- p6 s. w  O+ C! ^                                  AT590-BU-50000-r0p1-00rel0/logical/cortexm0plus/verilog/
95d54f552eade07ede322600da1f95c3  AT590-BU-50000-r0p1-00rel0/logical/cortexm0plus/verilog/cm0p_dbg_bpu.v
( @4 ~- Z* n; N5 b: c302c07875f4fc2cfe52c087ca6429cc0  AT590-BU-50000-r0p1-00rel0/logical/cortexm0plus/verilog/cm0p_matrix_sel.v
fce226f9ab48e92ff074fcad3dec6728  AT590-BU-50000-r0p1-00rel0/logical/cortexm0plus/verilog/cm0p_dbg_sel.v
# c, m9 `$ e, K6 Q, Fc00549e61aae47696609028230712dd6  AT590-BU-50000-r0p1-00rel0/logical/cortexm0plus/verilog/cm0p_dbg_ctl.v
ed481eab3481c71d4e2dc94531b88a3d  AT590-BU-50000-r0p1-00rel0/logical/cortexm0plus/verilog/cm0p_nvic.v
; I, U: T" Y) c57a19fb958028b39c425e6ac68f882aa  AT590-BU-50000-r0p1-00rel0/logical/cortexm0plus/verilog/cm0p_top_sys.v
66bc815f02ad900042cec326a6679963  AT590-BU-50000-r0p1-00rel0/logical/cortexm0plus/verilog/cm0p_dbg_dwt.v
62d60f5f2bceb3ce3f82e8fcb48446ff  AT590-BU-50000-r0p1-00rel0/logical/cortexm0plus/verilog/cm0p_mpu.v
# W+ [$ ?4 j# I" Z9 r4b054567197e5f54d3bacf492271f4c9  AT590-BU-50000-r0p1-00rel0/logical/cortexm0plus/verilog/cm0p_matrix.v
a436b897620bcd65a4f6f7d50345215e  AT590-BU-50000-r0p1-00rel0/logical/cortexm0plus/verilog/cm0p_top_clk.v