Cortex-M0+ IP Core

sinoicboy

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                                  AR085-DA-70000-r0p0-03rel0/
                                  AR085-DA-70000-r0p0-03rel0/doc/
                                  AR085-DA-70000-r0p0-03rel0/doc/ARMv6-M_architecture/
4af79e0557cc9c6863c2eab0f890aaad  AR085-DA-70000-r0p0-03rel0/doc/ARMv6-M_architecture/DDI0419C_arm_architecture_v6m_reference_manual.pdf
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                                  AR085-DC-11001-r0p0-04rel0/doc/errata/
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                                  AT590-BU-11001-r0p1-00rel0/
' P, E" w0 D& q+ s5 cb2bb2db05b71fa9e2ecd4c2841c22f3f  AT590-BU-11001-r0p1-00rel0/Cortex-M0+_Product_Errata_Notice_v4.pdf
' h/ G4 ]' O) {/ yd305236940b52b92b81e8579435efe7e  AT590-BU-11001-r0p1-00rel0/Cortex-M0+_Software_Developers_Errata_Notice_v4.pdf
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                                  AT590-BU-50000-r0p1-00rel0/
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                                  AT590-BU-50000-r0p1-00rel0/logical/
                                  AT590-BU-50000-r0p1-00rel0/logical/cm0p_dap/
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80fe9cfaeb5e260f70aebfcac0bdf888  AT590-BU-50000-r0p1-00rel0/logical/cm0p_dap/verilog/cm0p_dap_dp_cdc.v
063cdb1c994aca1f31971a3d52da426d  AT590-BU-50000-r0p1-00rel0/logical/cm0p_dap/verilog/cm0p_dap_dp_sw_defs.v
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db6b0ced453f9ba83035ca0b2d31c55d  AT590-BU-50000-r0p1-00rel0/logical/cm0p_dap/verilog/cm0p_dap_ap_mast.v
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! T( Q# [  F* [4 vbb3812a6b967f1ffaa604a858064f1d6  AT590-BU-50000-r0p1-00rel0/logical/cm0p_dap/verilog/cm0p_dap_top.v
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fce226f9ab48e92ff074fcad3dec6728  AT590-BU-50000-r0p1-00rel0/logical/cortexm0plus/verilog/cm0p_dbg_sel.v
c00549e61aae47696609028230712dd6  AT590-BU-50000-r0p1-00rel0/logical/cortexm0plus/verilog/cm0p_dbg_ctl.v
ed481eab3481c71d4e2dc94531b88a3d  AT590-BU-50000-r0p1-00rel0/logical/cortexm0plus/verilog/cm0p_nvic.v
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66bc815f02ad900042cec326a6679963  AT590-BU-50000-r0p1-00rel0/logical/cortexm0plus/verilog/cm0p_dbg_dwt.v
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$ D6 s! ^3 O' R' J# y: `9 U- A4b054567197e5f54d3bacf492271f4c9  AT590-BU-50000-r0p1-00rel0/logical/cortexm0plus/verilog/cm0p_matrix.v
a436b897620bcd65a4f6f7d50345215e  AT590-BU-50000-r0p1-00rel0/logical/cortexm0plus/verilog/cm0p_top_clk.v

114142500

thanks! do you have source codes for M0? It‘s very great for sharing the code。my e-mail is 114142500@qq.com,thank you very much!