Cortex-M0+ IP Core

sinoicboy

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( G* G/ M5 G  B8 u, q/ Ticonstart@gmail.com
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                                  AR085-DA-70000-r0p0-03rel0/
                                  AR085-DA-70000-r0p0-03rel0/doc/
                                  AR085-DA-70000-r0p0-03rel0/doc/ARMv6-M_architecture/
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                                  AR085-DC-11001-r0p0-04rel0/doc/
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                                  AT590-BU-11001-r0p1-00rel0/
b2bb2db05b71fa9e2ecd4c2841c22f3f  AT590-BU-11001-r0p1-00rel0/Cortex-M0+_Product_Errata_Notice_v4.pdf
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70404309a7929774e3bd8786e10771eb  AT590-BU-50000-r0p1-00rel0/ARM_Cortex-M0+_r0p1-30rel0_ReleaseNote.pdf
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c00549e61aae47696609028230712dd6  AT590-BU-50000-r0p1-00rel0/logical/cortexm0plus/verilog/cm0p_dbg_ctl.v
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62d60f5f2bceb3ce3f82e8fcb48446ff  AT590-BU-50000-r0p1-00rel0/logical/cortexm0plus/verilog/cm0p_mpu.v
4b054567197e5f54d3bacf492271f4c9  AT590-BU-50000-r0p1-00rel0/logical/cortexm0plus/verilog/cm0p_matrix.v
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114142500

thanks! do you have source codes for M0? It‘s very great for sharing the code。my e-mail is 114142500@qq.com,thank you very much!