What Verification IP do you plan to use MOST on your current design?

sophiew

Job Title igital verification Engineer
Job Category :Semiconductor
Location : Singapore
6 r' s7 {: J. d7 W8 S0 [" @Job Type : Permanent
) H0 w. A5 ~& R6 e  VJob Description:
Looking for SoC Verification Engineers Experienced in System Verilog Tools

Responsibilities:
Constrained-Random Verification using SystemVerilog.
Develop verification environment for DUT,Write and debug tests for DUT using SystemVerilog, Perl, and C.
Develop Bus Functional Model(BFM) or using Verification IP(VIP) for tests
# D; {1 p; i4 IDeveloping and reviewing test plans
& o* x! j* W1 b8 T9 |Write coverage monitors to evaluate the coverage of the DUT.
7 W) [3 T, E5 p) ~3 M; `Formal verification using SystemVerilog Assertion to verify SOC or IP is plus
6 J# s( U: X8 T3 J
, L4 ~% C2 C9 R. L6 ~6 e: NRequirements:
>4+ ethernet switch background
At least 3-year+ experience on digital design and verification
* C4 m! M9 g+ ~+ gExperience on SystemVerilog/VMM/OVM/UVM (UVM is plus)
Familiarity with transaction-level verification at higher-level of abstractions is plus.
Experiences in developing measurable verification plan.
Proficiency in UNIX scripting languages and utilities such as csh, sed, awk, and Perl.