FPGA-Based Prototyping on your current project

ranica

Hardware Applications Engineer – Cores

% [" N5 N7 k9 W0 R' C公      司：A famous IC company
工作地点：上海
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Job Requirements：
Qualifications
Good university degree, in Computer Science or Electronics Engineering ideally, although other science graduates would be considered if they have relevant experience.

$ \! K$ e" z  Z: |6 W# l' lExperience
   Minimum of 3 years industrial experience
- K) t5 \" @6 A7 B4 K' P   Strong understanding of XX processors
! ]+ O% [1 t3 p. T6 n( y6 U) z   Experience or knowledge of FPGA or ASIC design, simulation and/or verification techniques, including RTL coding and simulation, in Verilog or VHDL
   Understanding of FPGA or ASIC implementation flows (synthesis, scan insertion, layout)
   A good understanding of the interaction between software and hardware
   Demonstrable experience of problem solving and debug skills
   Experience of interacting with colleagues outside of China

ranica

Desirable
   Knowledge of XX architecture and AMBA protocol
   C/C++, assembler coding or other programming skills.
   Experience in integrating SoC peripherals

Personal Requirements
   Must be self-motivated, self-managing, responsible and proactive
7 h8 J1 u  w# J* A7 X% O   Must have excellent written and verbal communication skills with both colleagues and customers, including good written and spoken English
4 }' k9 Z  {0 _; P3 K   Must be proactive in obtaining engineering or management input, in order to complete project and internal tasks in a timely and accurate manner
   Must have the desire and ability to solve problems quickly
% R' }9 q& y- t# T' K   Must be enthusiastic and well driven
2 z% ~; V0 p. l$ K4 X* H   Must be able to schedule own workload and plan tasks – based on both internal and customer requirements.  
# I& g2 l1 [& \4 B4 l- h" [7 ~   Must have good inter-personal skills, and be able to work well within a team; especially when under pressure
" M, i7 W  ]) a6 H   Must be willing to be flexible and accept new challenges.
; t9 j  }1 a. t( n' B0 |3 H3 N" G   Must be able to travel on a regular basis, both to give customer training and also for internal business reasons.

ranica

Senior Digital Design Engineer
/ G( t0 L; E  n: U- H9 ?; G; ]; `
公      司：A famous European IC company
工作地点：上海
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$ P) s6 H$ I0 b4 W2 mJob description  
- define system partitioning of s/c circuits and system  
! f8 y1 m. p* C, L3 T; {( t- define HW/SW co-partitioning  
4 {9 j2 ^8 o: R0 }  ]) Q( @- @- provide technical feasibilities based on system simulation and/or FPGA based demonstrator  
3 y  s2 K  M0 u: {  P  L# C- propose new technical solutions on s/c and system level  
9 T9 T8 w4 |+ @: y0 s& j* M- design digital part of mixed signal (smart power) ASICs  
4 D  `/ |) B" s: g! z- close cooperation and interaction with international teams  
8 ?/ j0 h) a' T: {0 c+ a- coach junior engineers  
3 t4 w# q8 [8 W2 }5 D
7 D3 b- @3 H; n; ^Required knowledge competencies and attributes  
- master degree in microelectronic circuits or systems, Communications, Computer Engineering (or equivalent)
& w; T2 l7 M8 `2 h* y! r$ T+ k- > 5ys experience in digital design  
- good understanding of ASIC mixed signal flow (Cadence based)  
' N5 o( r* p% W  F( F# k; i5 R' W- strong background in HDL coding, verification and toplevel integration  
- H9 f9 s- K1 i  X- good understanding of communication interfaces used in Automotive (SPI, CAN, LIN, Flexray)  
2 u; m6 C  P6 U) @( \- experience in FPGA development  
4 W7 D  R# i! _# ?5 P- very good communication skills (written, oral)  
. D! W: X6 N3 J* B. D) w- self motivated and high level of flexibility  
  ^: v1 X3 y( X& ]- ~3 N5 m- foreign languages: English, German (not a must)