In your verification flow, the primary EDA vendor/tool your team is using

amatom

Staff Hardware Based Design and Verification Engineering Lead

公      司：One world top EDA company
工作地点：上海

+ i* q3 D' U/ }! l' R! S( M( E; VPosition Description:  
& p1 d& R2 H/ T$ k/ n1. The Staff Hardware Verification Engineering Lead will be in charge of a team of field engineers to support advanced hardware based verification flow integration engagements with Cadence customers and provide easy-to-adopt packages and workshops to xx  field application engineers and customers alike.
8 E2 I; u" g6 ^( K2 M* u1 W
2. He/she will focus on the technical aspects of the following hardware verification solutions for customer engagements as well as creating demos/workshops to train field AE and customers:
(1) xx  Palladium HW Acceleration Platforms
6 h2 A6 _( P6 s% V0 G$ r9 L4 I(2) xx Acceleratable Verification IP portfolio
(3) CVA product integration with other xx products such as Incisive Simulation and RTL Compiler for power analysis
2 J7 ^( ?% `0 `+ a  R# P# O(4) HW/SW Co-verification solutions for SoC designs

amatom

Position Requirements:  
. l' {0 v4 O1 j9 J$ v' m' Q. w1. Experience:  
- Minimum experience required: 10 years  
- Expertise in RTL top-down design and verification methodology automation are required. This includes full hands on knowledge of writing and debugging Verilog, VHDL and SystemVerilog based D&V environments.
- We would also like the candidate to have good knowledge of SoC design principles, embedded software development and HW/SW codesign and coverification.
  L" s* r$ c( Z- Knowledge of UNIX, C/C++, other scripting programming languages ( Perl, TCL…) is highly desired
$ S, `: s! I1 ^: O4 ~9 L- Strong verbal and written communication skills in English are required  
- HW acceleration or In-Circuit Emulation or FPGA prototyping experience is a must
6 [! b/ c( M5 T* V- Hardware verification, including knowledge of HDL simulators and debugging simulations
& j" [- K" S* O- Hands on experience with using design and verification languages like SystemC, SystemVerilog (IEEE 1800) and VHDL is a must.
+ h& ?: n- ^  X- R8 A( e% f- Knowledge of embedded systems and software development for SoCs is a plus
* K& z" _% t( R2. Education:  
3 x; w( b! F! n, `) sIdeally the person should possess the BS/BE level of understanding of CS or EE Engineering concepts  
- Minimum Education Required: education level of BS with 10+ years experience (or MS with 7+ or more years experience).
4 U+ P) Y8 D$ F0 q( {% z5 r7 I* r) i3. Travel of 30% of the time should be expected.