Which verification elements does your team use on your current design project?

ranica

Pls check all that apply, unless you don’t know?

ritaliu0604

Staff Hardware Based Design and Verification Engineering Lead

公      司：One world top EDA company
: c6 r8 R% p5 R) T8 I1 l: r工作地点：上海
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- I2 `' ^  w! S& E! M7 t* }' h( xPosition Description:  
0 _  X; M. \1 p3 D0 x1. The Staff Hardware Verification Engineering Lead will be in charge of a team of field engineers to support advanced hardware based verification flow integration engagements with Cadence customers and provide easy-to-adopt packages and workshops to xx  field application engineers and customers alike.

7 V: C$ d: Z' Z2. He/she will focus on the technical aspects of the following hardware verification solutions for customer engagements as well as creating demos/workshops to train field AE and customers:
7 t2 H( l' l! b1 `  ]) g(1) xx  Palladium HW Acceleration Platforms
(2) xx Acceleratable Verification IP portfolio
# k( @( r7 x; @- ~(3) CVA product integration with other xx products such as Incisive Simulation and RTL Compiler for power analysis
(4) HW/SW Co-verification solutions for SoC designs

ritaliu0604

Position Requirements:  
1. Experience:  
# P) g: I' y1 P, f8 I1 S- Minimum experience required: 10 years  
- Expertise in RTL top-down design and verification methodology automation are required. This includes full hands on knowledge of writing and debugging Verilog, VHDL and SystemVerilog based D&V environments.
0 `  X/ p' @3 `, q0 ^- We would also like the candidate to have good knowledge of SoC design principles, embedded software development and HW/SW codesign and coverification.
- Knowledge of UNIX, C/C++, other scripting programming languages ( Perl, TCL…) is highly desired
2 U3 A* H& j$ @2 B7 w- Strong verbal and written communication skills in English are required  
8 |3 d/ k$ ^' V! p0 U- HW acceleration or In-Circuit Emulation or FPGA prototyping experience is a must
- Hardware verification, including knowledge of HDL simulators and debugging simulations
- Hands on experience with using design and verification languages like SystemC, SystemVerilog (IEEE 1800) and VHDL is a must.
& H" B8 ?" [$ v: M4 n5 v' O- Knowledge of embedded systems and software development for SoCs is a plus
2. Education:  
Ideally the person should possess the BS/BE level of understanding of CS or EE Engineering concepts  
# g) @! b8 c  q" I6 H3 U- Minimum Education Required: education level of BS with 10+ years experience (or MS with 7+ or more years experience).
3. Travel of 30% of the time should be expected.

ranica

Senior Physical Design Engineer
公      司：A famous IC company
工作地点：南京
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6 r) K. s6 n$ T' Z, jKey Responsibilities  
Depending on experience, key responsibilities will involve some of the following:  
IC implementation from netlist to gdsii, with synthesis, floorplanning, place and route, timing closure, and physical verification.
) k# M7 B; o' E8 [! f( D" f0 p. ~As a key member of physical design team, your will work on one of most advanced and the most complex chip designed.
6 |% o+ G8 L9 N) U' DLeading a team of physical design engineers and resolving the technical related issues.  
* g9 Z3 Q) p6 e0 V  `Crosstalk analysis, power analysis, and static timing analysis.  
Write scripts in Tcl to improve productivity.  
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职位要求
3 ^+ Q( N$ X- T$ b$ G: z- P' M* jExperience: 5+ years in physical implementation engineering   
# m5 m3 d, K. w5 uEssential skills  
MS in EE required.&#8226roven track records of working independently on place-and-route project running and DRC/LVS/ERC/Antenna debugging skills  
9 Z6 ]4 o1 R. Z4 j* aExperience with Magma or Synopsys place-and-route tool set and physical design project implementation.  
& y5 N! f9 `& ]& U  t, aGood programming skill. Capable of writing Tcl or Perl.  
$ z1 ?) D9 [. M# k  sFamiliar with synthesis, static timing analysis.  
Self-motivated team worker, good verbal and written communication skills in English.  
: L* y1 _/ b5 x% h9 UTechnical and team leadership proffered. Previous management experience highly desired.  
/ @* ]) k; ~5 LExperience with synthesis, DFT, and verification is preferred.

innoing123

Mentor Graphics 與 TSMC 合作為10奈米推出 IC 設計和結束基礎架構
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% f& M0 ^- n  c. x5 G  ^4 @ 俄勒岡州威爾遜維爾2014年9月27日電 /美通社/ -- Mentor Graphics Corp.（納斯達克：MENT）今天宣佈該公司與 TSMC（臺灣積體電路製造股份有限公司，簡稱台積電）達成10奈米(nm) 的合作協定。為滿足用於早期客戶的測試晶片和IP（互聯網協議）設計起動的10奈米鰭式場效電晶體 (Fin Field-Effect Transistor；FinFET) 的工藝要求，已經改進了物理設計、分析、驗證和優化工具。基礎架構包括 Olympus-SoC™ 數位設計系統， Analog FastSPICE (AFS™) 平臺（含AFS Mega）和 Calibre® 結束解決方案 ( Calibre® signoff solution )。

( B7 a+ @* p1 K: l" \0 G' zTSMC 設計基礎架構行銷部 (Design Infrastructure Marketing Division) 高級總監 Suk Lee 表示：「TSMC 和 Mentor正在進行廣泛的工程工作，以便讓雙方的客戶都能很好地利用先進的工藝技術。每一個節點都需要進行許多創新才能滿足新的物理要求、提高客戶設計賦能 (design enablement) 的精確度，與此同時性能更優、轉回時間更短。」

Calibre 提供佈線形狀的全色彩能力，以幫助設計者指定符合10奈米規則要求的設計艙(cockpit)之外的色彩分配。針對制定積體電路佈線圖，改進後的Calibre RealTime 產品能進行互動的色彩檢查，同時利用晶片廠認可的Calibre結束平臺能使用所有制定佈線工具進行設計。

innoing123

針對10奈米  FinFET 設計，Mentor 和 TSMC 還改進了Calibre 填充解決方案。Calibre YieldEnhancer 中 SmartFill ECO 的功能支援「隨時填充 (fill-as-you-go)」工作流，以確保IP和其它設計模組在設計過程中都能準確地呈現。當部分設計被修改時，SmartFill ECO功能可重新填充僅僅受影響的那部分，從而最小化轉回時間 (turnaround time)。同樣的，為在諸如TSMC10奈米這樣的先進工藝節點上維持設計層級實現高效的佈線後模擬， Calibre LVS 也被改進了。
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兩家公司還聯手調整了 Mentor® Olympus-SoC 的佈線和路由系統讓它能滿足 TSMC 的10奈米 FinFET 的要求。為了能用於10奈米 FinFET，數據庫、佈線、時鐘樹合成、提取、優化和路由引擎都做了重大的改進。

為了確保10奈米 FinFET 設備的準確的電路類比，Mentor 與 TSMC 合作讓 BSIM-CMG（伯克利共多柵極電晶體）和 TMI 模型在 Analog FastSPICE 平臺（如AFS Mega）上能用於高速設備和電路層模擬。Calibre xACT™ 提取產品和 Calibre nmLVS™ 產品也支援新的10奈米 FinFET 模型。
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' H( _1 a+ j# H' U$ }- U3 P因Mentor 和 TSMC在設計賦能方面的合作讓客戶取得成功的案例，將於9月30日在San Jose Convention Center（聖若澤會展中心）舉行的TSMC的開放創新平臺生態系統論壇(Open Innovation Platform Ecosystem Forum)會議上講述。瞭解詳情，請參訪TSMC網站 www.tsmc.com 。