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RFIC工程師門檻?要當RFIC Designer的三大條件?

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1#
發表於 2013-12-26 10:14:11 | 顯示全部樓層
Field Applications Engineer
* Y$ Y, Q* }( m1 H" J1 a公      司:A famous IC company
; z* G( X9 l  U* H( Q3 z工作地点:深圳4 k4 n" b, i% R& H; n* M

/ R! v# t+ ]( E. ^7 mJob Description : U2 M9 L- u/ j8 [
Lead and manage a team of talented FAEs in supporting customer projects.  $ y8 a  v8 o/ }4 Y
Design or modify PCB reference design to implement preferred RF & BB IC layouts.  
( w' n( j' ^3 g2 n8 X- i8 c+ sWork with engineering to implement hardware QA procedures to satisfactorily test hardware releases in advance of shipment to customers. ) q& Q. {( D6 T
Debug customer hardware/firmware issues and track the changes through engineering. Document appropriate ECN’s within engineering or outside engineering services companies. , O  v5 q" X* a- i2 |0 `4 G
Write appropriate documentation to support ***’s development kits and reference designs. Create HW related customer support documents, application notes, and FAQs.
# s% U1 f! k* g- YWork with Engineering to implement hardware release standards and track hardware revision history among customers who have XX development kits and reference designs.
# y! M" }" C5 ~6 m  S/ r" qWork with the Sales and Marketing Teams to promote the company’s products and technology advantages. " {1 p7 Y* m: n. Y. j
Work with the Sales and Marketing Teams to qualify the technical feasibility of new potential programs.  ' V; m& f) z3 e' x1 c
Work with customers to bring programs from concept stage through to production.  ( t, f, j7 a9 ?, x! E
Work with customers and the internal Quality team to identify, debug and troubleshoot product quality issues.: y$ _  ^* H0 Z/ n

$ k1 t/ _3 J% U& CRequired Experience  8 \( U$ Z5 ]) D' f# }
BS or MS in Electronics Engineering.  
! j+ b# N, [8 p+ E4 n8 mMinimum of 10 years of hardware development and a minimum of 5 years experience in hardware semiconductor applications engineering , W1 J, ]( p% w- q* D" V& y6 Z
This individual must have experience working with customers in the early phases of development, and in particular, experience in defining Development Kits and reference designs is essential. : E" T/ T, P0 }1 T$ a
This individual must have experience working with customers in the early phases of development, and in particular, experience in defining Development Kits and reference designs is essential.
( ]; b0 D$ e3 a% t& X# q& K% t0 AExperience with communication IC’s, networking and video products are essential. Skills include hardware design, hardware support, IC debug, RF layout, development kit, and reference design support.
7 B7 o$ Q. `& OThis individual should be familiar with test equipment, schematic capture, and PCB layout tools, and production layout issues for mixed signal and RF systems. ) ]; f2 ~3 }0 K: ^2 a# P
Decent English communication skills in both oral and written.
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2#
發表於 2013-12-26 10:15:05 | 顯示全部樓層
Sr Analog Designer( F0 b6 W8 I/ U8 K; e5 X; J
公      司:A leader in high performance analog and mixed-signal IC design  t: f" d5 s- q4 I2 Z; X
工作地点:北京
% h* `! n% T- D/ T
9 t# \, b) Z9 ~' J. k/ wEducation and experience requirement , _' q2 o1 E, v: Z# b- o0 r& g7 t
o     PhD in EE, MSEE and 5+ years of and/or mixed-signal IC industry design experience; or BS and 6+  years of analog and/or mixed-signal IC industry design experience
" ^  B" o3 F4 eo     Hands-on CMOS product design experience in two or more of the following areas
  N# _' \4 P) s  M3 [6 m7 h2 Z' Mo       Receiver front end, including analog front-end, demodulation, channel selection etc.
7 r: b4 f- \( K7 Fo       High-precision ADC, including sigma-delta, pipeline etc 4 Z) ?+ }) Y( o  w/ t" _+ u
o       High-precision DAC
& j: a% G' S" }+ |, qo       Fully-differential continuous and discrete-time (e.g. switched capacitor) amplifier/filter design
' j) C, G; S6 e, R( _% vo       High-precision oscillator/PLL/DLL + ~  V8 ]0 ?& C6 y+ f+ h
o       Low noise voltage reference
8 R. w8 X1 P$ R& \3 Jo       On-chip high-voltage charge pump
# e$ [+ ?' `" Y  P5 Y- l3 A) B?      Experience in system level definition, modeling and verification a plus
% X+ i5 x, W. V$ l* j3 j  s?      Hands-on experience supervising layout and post-layout verification * d3 n6 {' s# m; g
?      Proficiency in tools
2 r  F; T& F% u, wo       Cadence design environment 0 U9 P5 l( [' {" U
o       Verilog/VerilogA/Matlab or other tools for system level modeling and verification  a plus
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3#
發表於 2013-12-26 10:15:56 | 顯示全部樓層
Sr Analog Designer
) c* x4 L0 z0 M' {8 G6 v公      司:A leader in high performance analog and mixed-signal IC design
, B$ l& d# `# u1 n+ P7 I工作地点:北京) V! H* d2 c, z& X& w7 c
: N$ _2 c4 G/ s9 `6 @& W* }5 W
Education and experience requirement 3 K: x9 Q6 z+ I
      PhD in EE, MSEE and 5+ years of and/or mixed-signal IC industry design experience; or BS and 6+  years of analog and/or mixed-signal IC industry design experience ) r# s( {' b, q( w( d# {$ h  R
      Hands-on CMOS product design experience in two or more of the following areas
5 ^5 q; M2 d$ o/ c  D       Receiver front end, including analog front-end, demodulation, channel selection etc. ) Q' Y/ {6 O, m& q+ P* D/ O. t, O
       High-precision ADC, including sigma-delta, pipeline etc
! g6 |: k& w% c' _0 j$ T0 i2 C8 O& s       High-precision DAC
4 a0 w. L, \! {0 l# k       Fully-differential continuous and discrete-time (e.g. switched capacitor) amplifier/filter design
* N7 ~+ X1 b4 @' j; r7 {* R& a' }       High-precision oscillator/PLL/DLL
1 W3 O- z' O% }8 Q/ `* D) v       Low noise voltage reference 9 p) I* {# J# h1 }' X
       On-chip high-voltage charge pump " x. U  _) q' D9 R
      Experience in system level definition, modeling and verification a plus 8 [+ b, `8 P) W2 F$ M4 R5 G8 N% K
      Hands-on experience supervising layout and post-layout verification
$ G: `) ~+ k/ H3 ^% n5 z3 d( {5 K      Proficiency in tools 9 H& \9 L3 _1 J  q" b
       Cadence design environment ' ]- B: d2 U) ?
       Verilog/VerilogA/Matlab or other tools for system level modeling and verification  a plus
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