電晶體即使有相同的W/L,也會因為電晶體Layout形狀不同,而受到不同的STI(shallow Trench Isolation)機械應力,6 M E; ?9 U4 i" J. \' h# A+ X
導致不同的電氣特性.NMOS drain current 會降,PMOS drain current 會升.做類比Layout時,要注意此效應.) H R/ H4 p. d, }. |
深次微米元件之間絕緣結構(Shallow trench isolation, STI)所引起的機械應力(Mechanical stress)變得更重要.
I think what you are asking about is STI stress effect, which means the device performance being changed by stress from STI. Generally, the STI stress impacts the MOSFET Vt (Ioff accordingly) & Ion by mobility degradation for NMOS (enhancement or degradation for PMOS, it depends) and species diffusion coefficient change. For some process, PMOS Vt would even change more than 100mV for short channel device. In BSIM4 SPICE model, the stress effect is modeled by mainly AA to gate edge dimension (along gate length direction). This topic is also briefed inside BSIM4 user manual. You can refer to it.
在同一半導體基板上製做複數個元件時,元件之間不應造成相互的影響(=寄生效應),因此必須在電氣上加以分離,這也就是所謂的元件分離(isolation)。元件的分離技術上雖有許多種,以下就其中的LOCOS與STI做簡單說明:$ }6 V# w. W$ |
LOCOS為Local Oxidation of Silicon(矽局部氧化法)的簡稱。首先使矽(Si)與氧(O2)在高溫下反應,形成名為襯墊氧化層的二氧化矽層(SiO2),這個SiO2層在之後的熱處理中具有緩和熱失真的效果。$ D. Y0 m; A! F( D) l4 Q' I
- u' A* f, L ^- {' `1 z6 ~STI則為Shallow Trench Isolation(淺溝分離法)的簡稱,與LOCOS相同,先形成氧化層與氮化層,依次除去分離區域部分中的氮化層與襯墊氧化層,並在其正下方的矽中掘一道淺溝(Trench),將矽基板暴露於高溫的氧氣中,再淺溝的內壁形成一層薄氧化層,其次,使硅烷氣體與氧氣反應,堆積出一層厚的氧化層將淺溝與以填補,使基板表面平坦化,將殘餘的氮化層予以去除,便可獲得埋設於矽基板表面上的分離用氧化層,由於STI較LOCOS之方法能夠獲得更為平坦的表面,能夠實現細微的分離幅度,分離能力高,因而為現今較先進的元件分離方式。 以上取錄自"圖解半導體"第十四章-86頁的部分內容~希望可以幫到你~ % t/ p. j+ r. r2 y; ]9 |PS:個人覺得圖解半導體這本書不賴~~推薦大家~有興趣的可以看看~