Chip123 科技應用創新平台

 找回密碼
 申請會員

QQ登錄

只需一步,快速開始

Login

用FB帳號登入

搜索
1 2 3 4
樓主: ranica
打印 上一主題 下一主題

[經驗交流] 台廠有哪幾家有設IC Design Quality Manager職務?何者最難?

  [複製鏈接]
1#
發表於 2014-3-11 13:09:36 | 顯示全部樓層
Product Engineer
) ~; U8 [8 M0 u1 C- W公      司:A famous IC company) ]7 C' A% K+ d$ h" j- x( T
工作地点:上海9 y9 p  c$ r: @7 T

* u# B4 J, m/ k; ]职位描述
1 ^, ?( O& @' ]- r2 ^4 G: p Ideal candidate will have completed BSEE , with 5 to 10 years experience in Semiconductor field.
  \8 D4 h# z* H# l, u4 B
" f+ a  T  K  Z% K4 J+ F Candidate should have strong oral and written communication skills -must be english speaking.
8 t$ V% u! l$ u1 ^- L; n' q3 P
- B7 G" U* M& T# \. I; [7 O7 |) o% y& q Candidate must have demonstrated strength with analog circuits, and familiarity with typical lab equipment such as scopes, DVM’s, curve tracers, and function generators. Strong bench skills are mandatory.( F7 H# N3 b+ }/ _: J% Y
5 s3 ]. ~! j2 |( b/ s' W
Ideal candidate will also have ability to debug IC’s to component level from design schematics and plots.
6 \3 S* j; P' i. N0 [
) r; r9 _: k% I8 f! ~: u Failure analysis background is a plus. # Q# j2 R% X% v9 g

% m5 \! V2 f1 P  ^ Candidate must also have ability to follow documented procedures, and must be able to work independently. Individual will report to management team in US.- g# g4 S' p, u. y# `# r

  T' [. C' p* W. s4 ]3 u9 l2 w3 a3 U7 O Job function to cover all aspects of New Product Development and Yield management,including bench-to-tester correlation, tri-temp characterization using ATE equipment, trouble shooting and yield management
回復

使用道具 舉報

2#
發表於 2014-3-11 13:10:23 | 顯示全部樓層
Hardware Engineer" R8 p$ o1 |8 k( a! o( P
公      司:A famous IC company
" [6 p+ J% L2 I6 t- R5 g, @# f工作地点:上海
: w/ f" v5 h: ]& S- G9 z" T; s2 I) z6 z
职位描述
! }* Y' ?; u2 u4 a4 e9 [1.Be responsible for hardware system design, discuss with chip designer, understanding their requirement and design the hardware system(schematic, PCB and C program) correspondingly
' H$ G. s8 E5 J2 h2. Testing the hardware system and provide test report 3 x, M' e( k& ~! g
3. Debugging the system, discussing with chip designer and help chip designer debug the issues  ; G( `. F+ d/ w- B, X% w& f2 O
7 t% `! ?/ w7 U* M- `' K8 r
职位要求:
& l, m+ {- f: k# ?/ w1 J1. B.S. in electrical engineering or equivalent is required 4 Y, m7 ]+ D1 o/ }  G/ M* F
2. 2 or more years of PCB design experience is required
. k' d# |7 u2 n3. 2 or more years of C programming is required ! @8 R! w6 g' n4 P% h+ ~
4. DDR knowledge and testing experience is required 7 N' \' L+ a& Y
5. Experience of Xilinx/Altera FPGA is preferred 5 s( k% m& F& P; e, T! |- f/ v
6. Experience of embedded system is preferred % h! f! r# ~4 B3 }- P% m1 A& M$ P* E$ {
7. Experience of using multimeter, waveform generator, oscilloscope is preferred  & Q/ Y( [9 a+ w- C
8. Verilog coding experience is preferred  
3 U1 B+ y  |" I+ T. x  
" f) U# T! U( d# P+ zPS:最好有 . DDR knowledge and testing experience is required
回復

使用道具 舉報

您需要登錄後才可以回帖 登錄 | 申請會員

本版積分規則

首頁|手機版|Chip123 科技應用創新平台 |新契機國際商機整合股份有限公司

GMT+8, 2024-5-17 03:02 AM , Processed in 0.107013 second(s), 18 queries .

Powered by Discuz! X3.2

© 2001-2013 Comsenz Inc.

快速回復 返回頂部 返回列表