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Staff Verification Engineer
( u8 Y% o, o/ `: M8 y( [7 o, s1 k公 司:one famous IC company0 L, q! {/ R6 v' \
工作地点:上海
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Qualifications
S7 x8 u8 @# [2 K0 `* k8 VMS in EE/CS/ME.
) k8 D& J& R# M n: {4 U, P6 fMinimum of five years experience.
# p5 U# }6 [: H- B4 ]5 N6 `- CAdditional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills.
t, |3 F: }: \! ICandidate should be familiar with as System Verilog, VMM/OVM/UVM verification methdology. % k; D8 G f/ y {& Y
Candidate should be familiar with industry standard ASIC design and verification tools and flow. 3 {* V" z) o* e) Y' U
Good knowledge ddr protocol and computer system achitecture would be an added advantage.
, A% e" u* |& @" f+ f) mGood knowledge of Perl and shell programming would be an added advantage.
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u" t5 [! i0 @6 j; JResponsibilities:
( q+ @( ^0 c4 D" A+ S" v- I2 d/ T' [: x-Understanding the expected functionality of designs.
- }, w2 r, w3 G7 Z# H-Developing testing and regression plans. 2 X: q% D% Q+ U) ?7 \
-Designing and developing verification environment.
6 P- y8 K9 c0 s-Running RTL and gate-level simulations/regression.
& \0 U; k5 F* Y8 T( z-Code/functional coverage development, analysis and closure.
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Requirements: / S8 y+ R5 K$ j$ |4 d
Experience & Skill: 5 Years
' Y1 ?) W2 \4 }-Design verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
" B: t7 Y& {2 _) f9 v" r. e-Knowledge in ASIC/FPGA design process and verification tools.
, B9 z" W- ~1 Z-Familiar with design and verification languages (Verilog, System Verilog, SVA etc.). ( p) Y% f; V, U5 @
- Scripting and automation skills (tcl, perl, makefile etc) a plus.
) f4 Q3 x! {; ~9 o& s2 x. n' D5 K-Familiar with C/C++.
8 W& U7 L8 N- C3 }7 O1 Z-Knowledge of DDR protocol a plus. 1 ^5 O% i8 j# x, h
-Independent and self-managing. |
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