|
Verification Engineer
L+ d6 X4 c7 U. u0 t% o$ [
2 @; Y1 x. I8 `公 司:A famous IC company
0 t$ R0 d& {7 p( o. v工作地点:上海" _8 u$ Y9 s; p# G8 G2 ` W
4 f: N- @: ^+ Z* JThe Role:
2 u: n& B) c, K/ P4 f' W% \: o, l· ASIC verification
. o7 J) _ p/ U" K· Work closely with the California teams + W. D2 H2 u/ O! C) j2 i3 I
· Support chip tape out and bring up 1 K) D r7 ?5 v* d; [
3 E9 F- y) {! U) g [
Requirements:
, G" ]9 ]* Q; o' d9 |9 @· 3+ years experience in ASIC Verification & N) p5 V0 ` J9 A
· BS in Electrical Engineering (or equivalent) is a must have, MSEE is desired
# t. o; J1 n9 v4 X g1 ~( V* y· System on Chip (SOC) Verification Experience, including AHB/AXI, CPU, Interface integration verification2 `7 f: [+ I6 f9 v& G( D
· Very familiar with verification languages – Verilog, System-Verilog, and VMM
B. H c: F m4 i· Test plan and test case documentation ! m3 e2 L8 T; ]1 _
· Functional coverage and code coverage analysis
$ C, a" |% P" R' i$ P· Must be familiar with various scripting languages used in verification, including Perl, Csh, Make, etc. 7 \6 b& n9 W! i
· Experience verifying interfaces such as PCIe, Ethernet, DDR, USB ' e* B' e4 l$ d
· Working knowledge of networking protocols 802.3 and 802.11, especially Medium Access Control and TCP/IP
, N% O: ~7 l: k3 [7 C$ M· Working knowledge of C programming language
" |3 N) Y! q- y9 G8 f4 w· Must be familiar with the ASIC verification flow from feature identification to test bench development and through final tape out sign-off 8 ^1 K& C- c3 X% X! _# A
· FPGA emulation experience a plus
) L7 _' j( _% t+ g, D# t7 q· Chip bring-up experience, including use of Logic Analyzer and Oscilloscope for debugging |
|