FPGA verification Engineer most difficult job functions?

ranica

招聘公司：A fabless IC design company
招聘岗位：系统产品经理
1 p6 w, c3 t! d+ C+ a工作地点：Beijing

岗位描述：
主要职责： 定制芯片的实际应用方案，为客户提供具体系统应用的解决方案，统计芯片在应用中出现的问题并形成改进建议书。
! y& {1 I5 ^8 p! e3 }8 k$ V6 |
职位要求：
5 c; f4 o& l4 u) L" w职位需求： 1. 计算机、通信、电子工程类专业，本科及以上学历。英语CET-4级以上水平，良好的英文读写能力； 2.了解民用消费类产品的框架结构及应用领域； 3. 具备较强的芯片级理解能力，对高速视频接口（LVDS, DVI, HDMI, DP）、数字电视相关芯片有深入的研究或应用，可以很准确的知道芯片的指标含 义和解释； 4. 熟练掌握 Cadence或PowerPCB/Powerlog ic等软件，熟知原理图设计，PCB 的布线规则和产品的生产流程。能够独立调试系统板级硬件； 5. 具备敏锐和快速的反应能力；良好的思维能力、信息收集、分析能力； 6. 良好的团队合作意识和沟通能力； 7. 适应经常出差，勤奋刻苦，爱岗敬业； 8. 具有较强的嵌入式软件编程能力，熟悉LINUX系统的应用。能够独立调试系统系统软件； 9. 具有产品应用及管理经历者优先。

ranica

招聘公司：A famous IC company
招聘岗位：SoC System Verification Engineer
工作地点：Xi'an

岗位描述：
Job Description: * Defines and develops system validation environment and test suites. * Hardware System Validation of Baseband ICs and peripheral for Mobile Terminals Technical coordination possible depending on experience and skills * Functional verification of the baseband IC and analyze of the occurring problems * Definition and implementation of test cases for the different modules(HW/SW, Low level drivers, Linux drivers) * Lead internal customer support during the evaluation phase * Interface to Concept Engineering Team, Design Team, SW Team

ranica

职位要求：
- h" g# I, S, ]8 Z, i# O6 X5 y3 WJob Description: * BS. or MS. Degree, MS. preferred, in Electrical / Electronics Engineering or equivalent * Minimum 2 years experience with the following tools/domains are recommended: * Knowledge of Embedded system * ARM Tools (ADS), GCC know how * Script languages (GNU Make, Make, Make File structures) * Debug Tooling Multi-ICE, Lauterbach, OS-aware debugging * RTOS Symbian, Nucleus, Linux or equivalent * Usage of C models (Virtual Prototype) to test Software before silicon availability * Configuration Management (Versioning Tools: ClearCase) * Knowledge of the following cores/architecture concepts are recommended: * ARM 7/9/11/Cortex Series and all controller functions: Interrupt/DMA... * Multimedia concept: JPEG, MPEG, Camera, Display, Multimedia Card Storage devices... * Standard Interfaces (UART, SSC, I2C, USB HS, USB FS, USB HSIC, MIPI HSl, SlimBus, MIPI Unipro¿) * Memory devices (DDR1, DDR2, SDRAM, Mobile RAM, NAND and NOR Flash) * Connectivity functions: WLAN, BlueTooth, GPS, FMR... * Good English, Excellent communication skill and team spirit oriented

ranica

招聘公司：A famous IC company
招聘岗位：Digital Design Engineer
工作地点：Beijing

0 h/ J' Y* F1 H* l岗位描述：
/ ?/ H! l" v" C7 o; C) k- Q5 tDuties · Digital design, including synthesis, timing simulations, power optimization, DFT · Mixed signal design; and verification · Define, develop, and implement characterization, test plans, test vector generation · Work with other division test groups inside/outside FSC to identify possible co-operative opportunities to optimize test solution · Work on the design of analog blocks like voltage regulators, I/O buffer, output drivers, voltage references, oscillators · Work with product definition; characterization, and test engineers in the full product development flow; Work with application & test engineers to define optimal design and characterization solutions, based on design objectives · Layout floor planning, including P&R, DRC, LVS, and LPE
- ^' {& M& c/ J- y7 `' c
职位要求：
5 t9 \3 t) v6 L- zRequirements · Minimum 3 years direct digital IC design experience · Minimum 3-5 years direct mixed signal IC design experience · CMOS mixed signal circuit design and proficiency with industry standard design tools and Verilog/VHDL · Knowledge in CMOS/BiCMOS Analog circuit design Experience in Cadence IC Design tool set, simulation, verification · Matlab/Simulink/VerilogA or other behavioral simulation expertise a plus Team-based, cross-functional organizational structure experience preferred · Excellent written and oral communication and presentation skills · Satisfactory written and oral communication skills in English · MSEE degree or above or equivalent experience · Strong communications skills; written, verbal, presentation and listening; · Good interpersonal skills to work in a team environment; · Good command of written and spoken English required; · Excellent interpersonal, written communication and presentation skills

ranica

招聘公司：A famous IC company
1 [9 t. ^4 k& j' F& m' ~$ e招聘岗位：Sr. Design Engineer
  B' x) b2 _3 n+ z2 w! `. @工作地点：Shanghai、Beijing
3 n, m7 h& Q4 h- ?. f
岗位描述：
1 Y: o" T5 w* l5 Z5 `' {Duties · Analog IC circuit design, simulation and verification · Design analog products and blocks such as high current or high capacitive load output drivers, operational amplifier, comparator, voltage reference, oscillator, error amplifier, voltage regulator etc. · Design of the switching power IC, DC-DC converters, for mobile/portal application · Evaluation, simulation and analysis of power architectures and circuit topologies · IC layout including floor planning, DRC, LVS, and LPE · Work with application and testing engineers to define optimal characterization and testing solution · Work with product definers and product engineers in full product development flow

0 m5 h' J1 X( S$ I  s  b. A3 D职位要求：
Requirements · Minimum 5 years direct DC-DC IC design experience, with MSEE or above degree · Strong knowledge in analog CMOS and Bipolar IC design · Working direct experience with switching power supplies, DC-DC converters, Battery charger, and their various topologies · Theoretical understanding of the power electronics, switching power supply topologies · Prior experience with power management related IC design a strong plus · Knowledge in analog IC layout · Matlab/Simulink/VerilogA or other behavioral simulation expertise a plus · Excellent written and oral communication and presentation skills · Satisfactory written and oral communication skills in English · MSEE degree or above or equivalent experience · Strong communications skills; written, verbal, presentation and listening; · Good interpersonal skills to work in a team environment; · Good command of written and spoken English required; · Excellent interpersonal, written communication and presentation skills

ranica

招聘公司：a top 15 semiconductor company
招聘岗位：Product Engineer
- v  N5 w8 r+ ?) L% K  Z工作地点：Beijing

) l8 N  e4 x1 \+ w0 b岗位描述：
/ W1 J  w- A9 f1 D9 q- Design database verification by simulation and on FPGA - Chip function evaluation - Develop test firmware and tools (Hardware and Software) - Develop evaluation board - Cooperate to debug chip issues - Customer support • Assist with customers’ issues • Visit customers and provide on-site support • Build up demo system
6 _& z& J2 z$ V8 C0 E  W$ H
职位要求：
" \$ R& k5 O$ C  q( c7 r4 k6 b- BSEE or above with minimum 3 years communication system experience - Familiar with Verilog. Has digital design experience with Verilog in real project - Minimum 3 years FPGA working experience, including code writing, timing analysis, debug - Familiar with at least one of schematic and PCB layout tools - Excellent English skill will be required. - Strong inter-personal, teamwork and communicational skills

ranica

客户 A famous IC company
2 p- Q1 b7 d+ U3 W地点 Shanghai

职位描述
We are looking for a person to join a design team to execute a state-of-the-art IC design project in the wireless communication field. Candidate must be familiar with digital IC design flow with a proven record of design and verification of a complex design project that led to successful silicon. Proficiency in Verilog is required.

职位要求
4 ~3 ?' c# W* ]8 sExperience in the following areas of expertise is desired:
Wireless media access control (MAC) design experience would be highly desirable
% |, N6 t6 [- m9 VKnowledge of TCP/IP and DMA Offload Engine design experience will be a plus
RTL design, verification, and chip integration
Experience in the following is beneficial but not necessary requirement:
' Q9 _1 F) L8 Y. X7 s+ v7 {Communication systems and RF systems
  v' ]& _! z4 c7 L) mFamiliarity with wireless communication systems and standards (802.11b/g/n and WiGig)
Knowledge of interface protocols such as PCI/PCIe would be a plus
FPGA design flow, testing, and emulation bringup

( W8 ?% C5 T' eOther requirements:
# K* k3 W6 T* N, }  I- Q6 jFamiliar with design and verification languages, EDA tools and ASIC/SOC design methodology
Good script language skill, such as Perl, Tcl and Shell
/ B9 p. f2 s; LGood written and oral communication skills in English
( k( t, c+ V2 nGood Team player
4 R8 W0 q1 ^% UCandidates must have MSEE degree with at least 5 years of experience

ranica

招聘公司：A famous IC company
招聘岗位：高级ASIC设计工程师
% c$ X$ R. j. t, s) @  P. e工作地点：Shanghai
& i' V8 S' A- n& S7 x5 M) \
岗位描述：
* l# A/ ~: E. J; x0 r  m: f: O1、定义设计模块结构并编写芯片设计规范； 2、使用VHDL/Verilog编写逻辑模块的RTL代码； 3、编写测试向量对模块进行仿真验证； 4、在FPGA平台上进行芯片级的测试验证； 5、进行模块级的芯片综合与时序分析； 6、编写完整的设计和验证报告。

职位要求：
& z8 {0 Q$ B) A1、具有电子或通信工程类硕士以上学历； 2、 熟练运用Verilog/VHDL进行芯片前端设计，熟练运用设计仿真综合和测试工具，如quartus，Xilinx，modelsim，nc，debussy，逻辑分析仪，信道仿真设备等； 3、深刻理解数字电路设计和时序分析方法，并拥有故障定位和解决问题的能力； 4、深刻理解通信原理、数字信号处理等基础知识，熟悉无线通信原理与常用算法； 5、具有3年以上芯片设计经验，拥有无线通信物理层开发项目（如DTMB、CMMB、DVB、3G, LTE等）经验者优先； 6、工作认真严谨，积极上进； 7、良好的团队合作意识和沟通能力。

ranica

Verification Engineer

, G$ u. S0 B2 t4 O$ i6 G5 z- I公      司：A famous IC company
2 Y( o7 W# t; T1 y工作地点：上海
* ]; Y" g5 y% l# n* U% Q
The Role:
·         ASIC  verification
9 b1 ~! u1 o" x0 w·         Work closely with the California teams
/ u  X+ m$ V# E3 R·         Support chip tape out and bring up

Requirements:
6 n3 v! r, u. Z* V·         3+ years experience in ASIC Verification
' B# ?$ V/ d: G: e( U5 r·         BS in Electrical Engineering (or equivalent) is a must have, MSEE is desired
·         System on Chip (SOC) Verification Experience, including AHB/AXI, CPU, Interface integration verification
·         Very familiar with verification languages – Verilog, System-Verilog, and VMM
·         Test plan and test case documentation
·         Functional coverage and code coverage analysis
·         Must be familiar with various scripting languages used in verification, including Perl, Csh, Make, etc.
& o6 u. \) v8 M' a: ?·         Experience verifying interfaces such as PCIe, Ethernet, DDR, USB
·         Working knowledge of networking protocols 802.3 and 802.11, especially Medium Access Control and TCP/IP
: G; U0 C$ ]5 j! w8 U* v9 }- F3 Z# i·         Working knowledge of C programming language
$ G  i$ [. d5 J·         Must be familiar with the ASIC verification flow from feature identification to test bench development and through final tape out sign-off
·         FPGA emulation experience a plus
·         Chip bring-up experience, including use of Logic Analyzer and Oscilloscope for debugging

ranica

ASIC Digital Verification Engineer
  B$ s- [+ |. s& l) s公      司：A mobile chipset semiconductor company
工作地点：上海
& B/ _1 `' ?3 R+ U9 b
Responsibilities:  
" o: v& v; C- K& t4 s$ {  Make verification plan for one module or whole chip.  
  Build up and maintain module-level and chip-level verification environment  
  Verify ASIC digital design based on case list, and output verification report.  
" e- \# `4 v% E' ^6 e3 l  Also responsible for lint checking and formal verification.  

& w  n; q3 Z4 _4 [Qualifications:  
  Proficiency in logic verification.  
  Experience with Verilog logic design language.  
  Experience with high-level verification languages such as System Verilog, System C, Vera or Specman e language.  
) w( e: ~$ m' p1 m8 R! l  Experience with UNIX/Linux simulation tools such as IUS or VCS.  
: R4 v5 ?: c6 l  Experience with C and C++ is a plus.  
  Experience with C_SHELL, TCL or PERL is a plus.  
  Experience with UVM, OVM or VMM is a plus.  
  Good knowledge of SOC design is a plus.  
  Good knowledge of software design is a plus.  
  Self-motivated and good team player.  
  MSEE or BSEE with 2+ years.

tk02561

Hardware Applications Engineer–Graphics
公      司：A famous IC company
$ z7 Q4 r; X: P) z/ B3 h工作地点：上海
, v* Q9 d% k' T
Desirable
Strong understanding of microprocessors
3 e1 ]- c, \! m- |6 Y& T# [A good understanding of the interaction between software and hardware
/ w; C9 o) N7 ]& f  }' QUnderstanding of FPGA or ASIC implementation flows (synthesis, scan insertion, layout)
C/C++, assembler coding or other programming skills.
Knowledge of GPU or graphics processing specification, like OpenGLES, Direct-X, is preferred

5 \& M+ p9 D/ g: GJob Requirements：

tk02561

Education
Good university degree, in Computer Science or Electronics Engineering ideally, although other science graduates would be considered if they have relevant experience.
  
Experience
Minimum of 4 years industrial experience
+ y/ y: h5 v5 c) ]* JExperience or knowledge of FPGA or ASIC design, simulation and/or verification techniques, including RTL coding and simulation, in Verilog or VHDL
Experience in integrating SoC peripherals
3 L1 l/ {3 A: ?1 k8 [$ O+ c0 O2 DExperience of interacting with colleagues outside of China
Professional experience of customer and sales interaction
* [( }4 h1 s3 _$ PDemonstrable experience of problem solving and debug skills
6 T& L! y, z, n: ]5 a* Z' ~- k
3 s- d: }' s2 c& vPersonal Requirements
Must have excellent written and verbal communication skills with both colleagues and customers, including good written and spoken English
7 p0 |8 ?1 F, O8 k) l2 xMust be proactive in obtaining engineering or management input, in order to complete project and internal tasks in a timely and accurate manner
Must have the desire and ability to solve problems quickly
4 b! \2 M% ?& m5 u( Q. H$ Y2 FMust be enthusiastic and well driven
; E* h3 {% d$ J* d& IMust be able to schedule own workload and plan tasks – based on both internal and customer requirements.  
Must have good inter-personal skills, and be able to work well within a team; especially when under pressure
) L. d- T+ N4 ]6 X; o; z8 N+ aMust be willing to be flexible and accept new challenges
2 [6 \1 X6 F; |0 J/ t" i/ H8 d3 k  nMust be able to travel on a regular basis, both to give customer training and also for internal business reasons.

ranica

Senior Digital Design Engineer
公      司：A leading semiconductor company
工作地点：香港

Job Responsibilities:
# G' T! N. I. h" y% R    Perform logic design, RTL coding, design verification, logic synthesis, DFT and static timing analysis
  ?# E2 }8 e# R, h    Develop verification environment and coverage closure
    Support wafer level testing and silicon evaluation
' B( e4 H7 v- J- J8 @    Prepare technical documents
' ^* i7 w. v3 {! f: h! k
' l" \9 ~0 }9 t8 K7 w, ]2 dJob Requirements:
    B.Sc or above in Electronic Engineering or equivalent. Applicants with postgraduate degree would be considered as an advantage
7 j, U5 ~7 d! Z8 J$ V* ^  a    5 Years or above of solid experience in one or more of the following areas: Verilog-based logic design and synthesis, constrained random    testbench with System Verilog & UVM, assertion based design verification or circuit-level SPICE simulations
    Knowledge of SoC and embedded system.
' e5 V% h$ [) L3 r3 T' n% P# |    Knowledge of scripting languages such as Perl, TCL and Make
    Candidate with less experience will be considered as Digital Design Engineer

ranica

数字IC验证工程师
3 t: v  q& @+ |: r8 v' b9 q* n$ _公      司：A famous IC company
. ?; }9 u) B2 C工作地点：上海

$ N# o4 d0 S! y岗位职责：
1、负责整个团队验证平台的搭建、维护
! A4 d3 T0 v7 w' F; L$ \2、先进验证方法和验证平台的评估、导入
9 Y! X1 z+ S" H, ]' ]2 x3、各种IP的模块验证，SOC相关的集成验证、系统验证，负责验证计划的制定实施、测试用例的编写。
  V5 m8 I4 D5 F% ~& s" O
职位要求：
4 w+ H( d* H: U5 [7 R: B) Q4 G- n1、大学本科及以上学历，电子、通信、计算机或微电子专业；
2、熟练掌握Verilog、SystemVerilog、C/C++等语言的编程，有扎实的数字电路基础；
4 z/ U3 j  t9 t6 K+ ~3、熟悉SoC验证开发流程，了解常用的验证方法学，如VMM等；
3、有1~2年芯片验证的相关工作经验；
4、具有较强的学习能力、沟通能力和良好的团队合作精神；
5、有基于ARM处理器的SOC芯片验证经验者优先考虑。

jcase

数字IC验证工程师
公      司：A famous IC company
工作地点：上海
) S- M- F% i8 R8 L" w7 G5 E' Y
& {& ~' f' V5 I7 C" Y# c) [+ i岗位职责：
$ L3 _9 X; U/ W; r: d1、负责整个团队验证平台的搭建、维护
/ d" a  T2 e' D2 ~9 }2、先进验证方法和验证平台的评估、导入
3、各种IP的模块验证，SOC相关的集成验证、系统验证，负责验证计划的制定实施、测试用例的编写。

职位要求：
; ~# D$ H5 `6 {& v/ e/ h1、大学本科及以上学历，电子、通信、计算机或微电子专业；
2、熟练掌握Verilog、SystemVerilog、C/C++等语言的编程，有扎实的数字电路基础；
1 M6 J) F# D2 u" A* J" b3、熟悉SoC验证开发流程，了解常用的验证方法学，如VMM等；
3、有1~2年芯片验证的相关工作经验；
' }0 A: H, l7 c/ a8 x4、具有较强的学习能力、沟通能力和良好的团队合作精神；
5 r$ Y9 s; r0 j! j5、有基于ARM处理器的SOC芯片验证经验者优先考虑。

ranica

Senior Digital Design Engineer
& B/ i' P; A2 ~1 u- A公      司：A famous European IC company
工作地点：上海

Job description  
- define system partitioning of s/c circuits and system  
8 r8 t2 t. j. }' f: ^4 Z  ~. l8 B- define HW/SW co-partitioning  
0 x! \* o- f' {2 w( D, f5 B- provide technical feasibilities based on system simulation and/or FPGA based demonstrator  
- propose new technical solutions on s/c and system level  
  s: }) A9 @; _0 V- design digital part of mixed signal (smart power) ASICs  
- close cooperation and interaction with international teams  
- coach junior engineers  

Required knowledge competencies and attributes  
, @3 Z. F: z4 u6 X- master degree in microelectronic circuits or systems, Communications, Computer Engineering (or equivalent)
# B1 g7 w4 R- c- > 5ys experience in digital design  
! j6 s) N+ }- {3 d! P- good understanding of ASIC mixed signal flow (Cadence based)  
# `# S. P4 B: R2 k+ x  R- strong background in HDL coding, verification and toplevel integration  
& B) t$ J8 l9 K+ u9 q- good understanding of communication interfaces used in Automotive (SPI, CAN, LIN, Flexray)  
: P& p$ E3 k  }8 ~5 J$ C: C- experience in FPGA development  
, M. ]' Y2 ?) n+ ?! c, G- very good communication skills (written, oral)  
- self motivated and high level of flexibility  
; G% x. Z0 r- M- foreign languages: English, German (not a must)

sophiew

数字IC验证工程师
公      司：A famous IC company
工作地点：上海
+ P; U/ m  z$ c1 d8 t* x
岗位职责：
1、负责整个团队验证平台的搭建、维护
; w5 r- o: b( p' X. n2、先进验证方法和验证平台的评估、导入
3、各种IP的模块验证，SOC相关的集成验证、系统验证，负责验证计划的制定实施、测试用例的编写。

4 A  h+ l) Q& J' r' l6 G. ~职位要求：
1、大学本科及以上学历，电子、通信、计算机或微电子专业；
2、熟练掌握Verilog、SystemVerilog、C/C++等语言的编程，有扎实的数字电路基础；
3、熟悉SoC验证开发流程，了解常用的验证方法学，如VMM等；
0 P9 t5 {# Q8 \# N2 P3、有1~2年芯片验证的相关工作经验；
4、具有较强的学习能力、沟通能力和良好的团队合作精神；
5、有基于ARM处理器的SOC芯片验证经验者优先考虑。

ranica

ASIC Verification Engineer (WMAC)
* W0 l1 G1 S% H9 r公      司：A famous IC company
工作地点：上海
, a% @* O: C9 p2 P2 [( E' s9 i
The Role:
  Q" S  I' m- X8 A9 Q        ASIC design and verification
        Work closely with the California teams
$ c1 ]( Y7 H9 B8 Y5 \3 i' w        Support chip tape out and bring up
7 C1 S6 W3 e' U5 T4 C1 y
, S7 {: ^4 y/ M: p) g/ g. gRequirement:
0 }6 T3 \9 p" o; E6 M( U        8-10 yrs. experience  
6 e$ ?. G. `( _" }/ q8 r. ^        Knowledge of Verilog / System Verilog & Perl
& I0 ^( l, N! m$ t' R        Has worked on complex project; experience with 802.11 is preferable
        Can work independently - want him to take over MVE
+ v8 V. `1 a( X# E        Experience in Networking SOC, Ethernet MAC or any other MAC layer protocol experience is plus

ranica

ASIC Digital Verification Engineer
; I. h( G2 X: Z- u" H公      司：A mobile chipset semiconductor company
) `. ?5 l6 X& J" b工作地点：上海
" k1 {5 q5 J4 h  Z, I) `
) y) H  A2 s8 aResponsibilities:  
! \& f& ?) K3 }" _# o  Make verification plan for one module or whole chip.  
' s3 f# W, O4 z, g- M  Build up and maintain module-level and chip-level verification environment  
( l3 z8 a0 C. l$ j2 L; d! G+ G  Verify ASIC digital design based on case list, and output verification report.  
- K6 l+ x9 L, W- w0 m6 G: h3 u: B  Also responsible for lint checking and formal verification.  
  _0 W) i0 N: s: ?% K
Qualifications:  
1 `& Y! D: o9 p: F' o  Proficiency in logic verification.  
+ [+ Y+ @6 B8 x( ^- _& n  Experience with Verilog logic design language.  
  Experience with high-level verification languages such as System Verilog, System C, Vera or Specman e language.  
) u9 n6 ?* `# a  v! k* R" v  Experience with UNIX/Linux simulation tools such as IUS or VCS.  
$ ^+ A- n7 k2 g, F/ L$ ~  Experience with C and C++ is a plus.  
  Experience with C_SHELL, TCL or PERL is a plus.  
  Experience with UVM, OVM or VMM is a plus.  
  Good knowledge of SOC design is a plus.  
  Good knowledge of software design is a plus.  
  Self-motivated and good team player.  
* R$ Y% N0 [" l" k* U3 C  MSEE or BSEE with 2+ years.

ranica

Staff Verification Engineer
1 p6 H$ o2 _' c6 z公      司：one famous IC company
工作地点：上海
5 L, Y# O) i# ?6 ~/ O
Qualifications
5 w0 l3 r0 N; N' a( FMS in EE/CS/ME.  
Minimum of five  years experience.
Additional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills.
) ^9 o/ x1 F- ECandidate should be familiar with as System Verilog, VMM/OVM/UVM verification methdology.
Candidate should be familiar with industry standard ASIC design and verification tools and flow.
Good knowledge ddr protocol and computer system achitecture would be an added advantage.
3 }, i3 U- K' t7 D: @Good knowledge of Perl and shell programming would be an added advantage.  

Responsibilities:
-Understanding the expected functionality of designs.
-Developing testing and regression plans.
  E6 w: ^) G6 B: I1 V! E-Designing and developing verification environment.
-Running RTL and gate-level simulations/regression.
/ X* ]' d8 I4 P+ {0 V$ F-Code/functional coverage development, analysis and closure.

, f7 A8 t- O( X7 N# y8 Z& J& PRequirements:
Experience & Skill: 5 Years
) c6 _- ~: z4 K3 b% A4 m-Design verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
-Knowledge in ASIC/FPGA design process and verification tools.
-Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).
- Scripting and automation skills (tcl, perl, makefile etc) a plus.
8 j, H1 N& C/ I7 u& O- T+ u6 Q-Familiar with C/C++.
-Knowledge of DDR protocol a plus.
-Independent and self-managing.