FPGA verification Engineer most difficult job functions?

ranica

Staff Verification Engineer
  c. Y. w; o- R% |- ~
& w, ~( e" _5 z5 A0 U" S* c公      司：one famous IC company
7 j% s5 u, J$ {9 c  R工作地点：上海

; L( I7 N+ H, E$ KQualifications
MS in EE/CS/ME.  
  W9 U, l$ c! C# Y- WMinimum of five  years experience.
Additional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills.
1 d3 U1 u8 W: t( oCandidate should be familiar with as System Verilog, VMM/OVM/UVM verification methdology.
Candidate should be familiar with industry standard ASIC design and verification tools and flow.
Good knowledge ddr protocol and computer system achitecture would be an added advantage.
8 M- T$ h2 u( b# m# Y' a1 ?# f3 hGood knowledge of Perl and shell programming would be an added advantage.  

) G* O$ F" {7 r0 t5 Q- B: r3 r1 yResponsibilities:
! O  o& ^9 m& v6 F# p. O9 G: d' A-Understanding the expected functionality of designs.
# o9 [* ], G" j* p# M' m, Q) Y8 [-Developing testing and regression plans.
-Designing and developing verification environment.
* g2 u3 q5 Y( w) l- v7 Y-Running RTL and gate-level simulations/regression.
-Code/functional coverage development, analysis and closure.
  A& h: M- ~: b9 v8 t( t- k" V
Requirements:
Experience & Skill: 5 Years
4 b/ Z. A8 y5 W# e$ [; @7 c-Design verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
, W2 Q0 I4 O, W-Knowledge in ASIC/FPGA design process and verification tools.
9 F8 _! J% A) c9 c, m2 Z: a-Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).
7 J* k6 H# B& l% z- Scripting and automation skills (tcl, perl, makefile etc) a plus.
-Familiar with C/C++.
-Knowledge of DDR protocol a plus.
( W+ z2 \: O, Q2 a% ]-Independent and self-managing.

ranica

Digital Design Engineer
) q4 L) M( O, Y, }! _( E
公      司：A famous IC company
工作地点：上海
( Z) Z7 G+ k0 S
Duties
Work with internal and external customers to understand product requirements.
1 {' A- {# U" r; ?$ j# ]Create critical silicon technologies to meet the product requirements.
Work out critical design flows and methodologies to execute implementation flawlessly.
9 M3 X. K+ ?: k, ~Design and deliver final design through multiple stages like specification, micro-architecture, IP  development, RTL coding, verification, logic synthesis, DFT, timing convergence, as well as helping on physical implementation.
Complete full documentation.
. ?3 M4 {8 |  I* T- Q" vHelp and mentor junior engineers.

" U5 Z! B  [" o& M; L( cJob Requirements:  
% t( Q5 E1 Y) r8 `Solid understanding of all SoC chip development stages is required.  
Hands-on Experience with complex SoC design flow is required.  
Hands-on Experience with RTL coding, simulation, verification is required.
8 m* J+ K+ L6 P2 e! Z. \1 OExperience with DFT and timing tools is preferred.
$ K+ p1 Z( p( t+ ~. X3 I2 C4 C7 {Experience with ARM platform is preferred.
Experience with low power design flow is preferred.
' Z' P- v% Y, C1 BExperience with system verilog is preferred.
Good organization and documentation abilities  
# z/ C6 a4 o" [) LMS in Electrical Engineering and Computer Science with 4 years of experience in SoC design

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