FPGA verification Engineer most difficult job functions?

ranica

Staff Verification Engineer
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公      司：one famous IC company
7 ?0 F4 S0 Z3 v/ J9 g工作地点：上海

Qualifications
MS in EE/CS/ME.  
5 n: K) b4 c8 a& s8 hMinimum of five  years experience.
) X9 }' x* ?/ T6 mAdditional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills.
Candidate should be familiar with as System Verilog, VMM/OVM/UVM verification methdology.
Candidate should be familiar with industry standard ASIC design and verification tools and flow.
$ M  R; f0 ~5 h6 RGood knowledge ddr protocol and computer system achitecture would be an added advantage.
9 n; U5 [8 R' B  J# o1 V' d# fGood knowledge of Perl and shell programming would be an added advantage.  
4 r$ m8 K$ I  I1 l
7 _: a; g! m, A( N7 @7 j) A' ?Responsibilities:
-Understanding the expected functionality of designs.
, t' O& Z! n* g4 v9 i- y- p-Developing testing and regression plans.
% q; O( l0 H/ Q& {7 A1 K  P5 d-Designing and developing verification environment.
-Running RTL and gate-level simulations/regression.
5 |4 o* Q* `3 W; M* f-Code/functional coverage development, analysis and closure.

Requirements:
! a" s7 R0 g; y: o" a- `9 V( wExperience & Skill: 5 Years
! O! {# b1 N% e1 Y, p$ h-Design verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
-Knowledge in ASIC/FPGA design process and verification tools.
2 l# F- m" e  n' m9 a# T$ |+ r7 p-Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).
* O' l6 Y* y9 k% b. \( l- Scripting and automation skills (tcl, perl, makefile etc) a plus.
7 w% k- n+ p7 ?( e- @( h6 A) ~4 {-Familiar with C/C++.
. s1 D( s: g  G. |  ^-Knowledge of DDR protocol a plus.
  {! B3 j! q7 I" Y-Independent and self-managing.

ranica

Digital Design Engineer

公      司：A famous IC company
工作地点：上海
9 H  q% E7 ]7 x$ w
Duties
5 w- s2 @/ y3 S' X3 ~  b! MWork with internal and external customers to understand product requirements.
Create critical silicon technologies to meet the product requirements.
Work out critical design flows and methodologies to execute implementation flawlessly.
8 Q$ Z1 d& Q/ k+ S6 z: I4 t0 aDesign and deliver final design through multiple stages like specification, micro-architecture, IP  development, RTL coding, verification, logic synthesis, DFT, timing convergence, as well as helping on physical implementation.
Complete full documentation.
Help and mentor junior engineers.
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1 s: G) {9 ^! K$ R% v$ l' g( d+ kJob Requirements:  
Solid understanding of all SoC chip development stages is required.  
/ ?* l- m, W# C# q  hHands-on Experience with complex SoC design flow is required.  
Hands-on Experience with RTL coding, simulation, verification is required.
& ]% C) A% y/ S, R( Q, z2 S/ V, U% G4 RExperience with DFT and timing tools is preferred.
' G# y' x4 n% t6 [7 NExperience with ARM platform is preferred.
Experience with low power design flow is preferred.
7 B& {6 C# q. E# I* {! zExperience with system verilog is preferred.
Good organization and documentation abilities  
/ X; h7 R: k) A: h: A3 EMS in Electrical Engineering and Computer Science with 4 years of experience in SoC design

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