When PCB layout area is not enough, we often use 4mil GND trace to shielding RF clock trace with 4mil spacing.7 M- Q0 o# A7 ]4 ~5 E4 z8 @
Is this way enough to avoid RF clock signal to couple other signal trace near the 4mil trace? : ~3 S5 F4 v. ~7 H- A3 i& w3 g2 GThanks
u r proposed to refer to 3W rule. & ]+ a6 g) m: z* S7 A8 a
when clock trace is 5 mils, u will need 10 mils spacing. 9 k5 H* l( X" s+ Yof course GND trace will help, but PTH through holes with proper interval will do it better.! |- v" R# x1 g& V% H, @8 [( N, P% z
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google it for detailed information, please!