When PCB layout area is not enough, we often use 4mil GND trace to shielding RF clock trace with 4mil spacing. $ z, n) ~2 U' }1 O" WIs this way enough to avoid RF clock signal to couple other signal trace near the 4mil trace?/ L" c7 A, }9 Y; b( T2 O! u
Thanks
u r proposed to refer to 3W rule. 7 h y" ?/ J0 M: M6 pwhen clock trace is 5 mils, u will need 10 mils spacing./ G: S# ~6 T5 h$ S- M8 L3 s- }
of course GND trace will help, but PTH through holes with proper interval will do it better. 7 J- q, e0 v3 M* i- c 2 q" H+ Z& F( {" y a: x! }google it for detailed information, please!