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補充:
: d8 t( Y& l Z% ?# v1. Reference Library: the reference libraries or Process Design Kits (PDK) where the symbol views of master cells are present. 既你想要用的symbol是來至哪個 library.1 l- j0 A# }% z, s# B) a* j
2. Syntax for Specifying Device Maps in a Device-Map File:
6 H4 q- J0 `" k devMap := <primitive_device_name> <mapped_device_name>) Z4 K. J i- a/ m( h" F- m: L
[ propMatch := list_of_prop_to_match ]
d% [" ~& V; z# F [ termMap := list_of_terminals_to_map ]
8 B% z# X3 B( ]) }- z# @% |/ ` [ propMap := list_of_properties_to_map ]" i ?7 t" f9 n
[ addProp := list_of_additional_properties_to_map ]2 R, P: L" s: ]! O7 E( R
Example:
) H+ g1 v& E. D' L devMap := resistor res; o O& n) w* @6 w! _* g
propMatch := r 20000
: \! K, i# L1 y0 a% J+ | termMap := PLUS PLUS MINUS MINUS4 B9 m4 ^7 n! J& ?; I" _- e }
propMap := subType type r resVal w width l length
0 [- w# N' F8 N6 S addProp := model res |
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發表於 2012-6-5 09:02:02
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