Layout Optimization on ESD Diodes for Giga-Hz RF and High-Speed I/O Circuits

semico_ljj

Layout Optimization on ESD Diodes for Giga-Hz RF and High-Speed I/O Circuits

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sslin

謝謝大大的分享~~知識因分享而壯大！

5 v9 K+ \$ [8 y/ h$ N~只有站在巨人的肩膀上才不會被食人族吃了!

zhifj86

thank you very much for your sharing

oscargo

正為ESD耐受度傷腦筋----

linger809

Abstract -- The diode operated in forward-biased condition has
been widely used as an effective on-c ...
semico_ljj 發表於 2010-6-25 08:50 AM

2 r8 q6 {9 R* J+ N6 ?+ f5 e2 q

不知道这种形式的ＩＯ有没有经过测试，实际的效果和预想的有多少的差别，thanks!

oika_51

看起來有幫助
) a. ^0 @9 E8 w- v* d& c# Z感謝分享

caesarxl

谢谢楼主分享，非常感谢

linyuejing

下載來看看
6 b; v2 p, T6 h! H. G0 h. f$ l下載來看看
- F. m$ p5 ~' D( k9 s" J下載來看看
下載來看看
應該有幫助
謝謝囉

xp212125o

看起來有幫助
8 r4 e/ V; J) e% j- V感謝分享
- o, r' G6 V; z/ @6 k( H先下載來看看
/ f( H3 a' E9 r2 n! @& sthank you ~

semico_ljj

Abstract -- The diode operated in forward-biased condition has
been widely used as an effective on-chip ESD protection device at
$ a$ V) b' v! R/ t- k* Y/ kGHz RF and high-speed I/O pads due to the small parasitic
loading effect and high ESD robustness in CMOS integrated
4 X$ P; H; Z) b- r" G2 M5 S, A% acircuits (ICs). This work presents new ESD protection diodes
realized in the octagon, waffle-hollow, and octagon-hollow layout
styles to improve the efficiency of ESD current distribution and
7 E9 X3 [; ]* U3 G$ B$ R$ Pto reduce the parasitic capacitance. The new ESD protection
" {) T/ g  k0 L. J: |( Pdiodes can achieve smaller parasitic capacitance under the same
- g- D7 B7 h0 x7 L  ?5 o7 K7 |ESD robustness level as compared to the waffle diode. Therefore,
/ y# n5 S" G; A3 Wthe signal degradation of GHz RF and high-speed transmission
can be reduced due to smaller parasitic capacitance from the new
5 K0 s6 s" ^8 `- tproposed diodes.