http://www.fpga4fun.com/forum/vi ... 0fdec8d259da2ea79d2 % D3 N& {/ R3 ?* N F1 L7 E1 x0 M! l! o2 z3 U+ Q% p( G9 u
I had to do a couple of things to get it to work & t! V# l. v% P4 t0 U1) needed a valid license file - G t' E* g7 I7 C1 }2) Name of the Verilog HDL should be the same as the module specified in the actual code & s' C- E& m! y6 ^4 W3) Compile first (Processing->Start Compilation to get the node list to populate in Pin Panner(in All Pins List)