How verilog HDL to schematic?

sieg70

若不是用CPLD/FPGA, 那意思是要下線作ASIC囉?
- q2 |) z4 `% {; p/ d( J+ }
: A+ {( A8 l5 j; I. P那可能要跑跑cell-based design flow.

Design Compiler也可以派上用場