請問由Verilog code到IC layout 需要哪些軟體

leesg

問題, 已完成 Verilog code 設計, 模擬(ModelSim)
想要用軟體直接 run 到 IC Layout 產生 die photo,
7 ^) ?8 n- {% s4 F8 r, s5 M/ M4 i要用什麼軟體組合 ? (輸入 verilog code, 自動跑出 IC Layout)
7 n( h* q% _& y0 z8 ~& o: q1.
design compiler + Astro ?
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0 I- Y9 W& z& c# l# F- G" g9 Msynopsys IC compiler ?
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3.
cadnece virtuso ?

lee100

Synopsys R2G flow
& g: k9 h" Y. a4 C, z; L1 K+ o0 r1. rtl simulation by vcs
2. synthesis by design compiler ultra with dc/dct mode
3. dft insertion by dft compiler
4. jtag insertion by bsd compiler
$ F- R2 }/ H) e# G2 g* _8 n5. ICG insertion by power compiler
6. pre/post-layout STA by prime time
7. pre/post-layout power analysis by prime time px
8. PnR by IC compiler
3 a& z7 k2 r; u9. post-layout SI analysis by prime time si
10. post-layout simulation by vcs

putechen

sometimes ,star-RCXT is necessary.just for layout PEX.

yytseng

after above place and route task, you need virtuoso or laker to merge cell layouts and do some editing.
4 V( l; Y( v/ }0 sclean up LVS/DRC/ERC/ESD violations with calibre or (hercules, assura) tools.

ejean

1. magma is another solution
2 q2 s% ~' @2 V0 G2. Astro  from synopsys
3. FirstEncounter from Cadence
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All with basic DRC and LVS, you have to run Calibre, etc. to finish the final verification.

ilovepachaya

私心推薦APR使用IC Compiler  效果很好