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Synopsys R2G flow
& k3 T# E" f. l; @$ x+ d1 w! ?) h! v1. rtl simulation by vcs2 @& M( y. W" z. h
2. synthesis by design compiler ultra with dc/dct mode
6 K. x5 r, c! [2 B3. dft insertion by dft compiler2 I& s, ?9 [ ~
4. jtag insertion by bsd compiler' D" v7 n! A* p# m" j- ]
5. ICG insertion by power compiler1 G0 B, h+ {/ Y* N) c, s+ \& B* r
6. pre/post-layout STA by prime time
9 R9 p0 f+ r1 Q' y7. pre/post-layout power analysis by prime time px
% N: S* l7 I+ K* v8. PnR by IC compiler
$ j I) ?! h: ~: H8 j+ s9. post-layout SI analysis by prime time si
7 | ?( U6 d1 Z1 u10. post-layout simulation by vcs |
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