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Analog / Mixed Signal Examples7 ]2 Z; W d: Y% @, m
" Z0 O& R" d/ B v6 F( `' |Behavioral Models of ADCs& [& l7 }. Z' \! I0 `% j% @
\ams\sampling\; sampling_101;- L4 `1 x9 p4 O' O
Sigma-Delta ADC 1st order modulator $ cd \ams\adc\; dspsdadc2;
' I9 D" a$ O8 N" n4 g Sigma-Delta ADC 2nd order modulator $ cd \ams\adc\; dspsdadc3; " @, m. I P0 n4 a, I( G" C
Sigma-Delta ADC 2nd order modulator discrete time (switched capacitor prototype) $ cd \ams\adc\; dspsdadc4;
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Behavioral RF
0 m2 B' O6 ?% A* W' |" \% { Measurement of Lowpass Filter Freq Response $ cd feed_fwd_2;: \4 V# g) O& _$ q% L6 Y: \4 T
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PLLs
9 S' ^9 o4 y9 N- w! X VCO with phase noise $ cd
- S- `5 _% p) g7 m Pll with freq domain instruments $ cd \ams\pll;
; h' W# ~0 n/ ? Pll fractional with analog compensation $ cd \ams\pll; 1 U0 _- m- w$ A4 I# ]& u
Pll fractional with digital compensation $ cd \ams\pll; 6 ]) q) l- b/ C3 ~4 g" D
Pll optimization (Nonlinear Control Design) $ cd \ams\pll;
; S, Z1 E+ O! B; ^5 V7 F7 e Carrier and Symbol Timing Recovery (NCO->ADC) $ cd \ams\pll; carrier_timing; , N0 m2 G9 F# ] i, ]
Carrier and Symbol Timing Recovery (Fractional Delay) $ cd \ams\pll; timing_recovery_1; |
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