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Analog / Mixed Signal Examples
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Behavioral Models of ADCs
+ k6 X( H1 H- l/ @' [+ E" Q# t\ams\sampling\; sampling_101;
' z) D* Z9 M/ B- V Sigma-Delta ADC 1st order modulator $ cd \ams\adc\; dspsdadc2; # ]( q, \2 u" p# x8 @# P1 J7 `
Sigma-Delta ADC 2nd order modulator $ cd \ams\adc\; dspsdadc3; * m; N! z0 ~3 R5 K7 X
Sigma-Delta ADC 2nd order modulator discrete time (switched capacitor prototype) $ cd \ams\adc\; dspsdadc4;
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& d- A0 G0 h4 F# fBehavioral RF/ v/ D2 [/ [9 u/ q/ E' k l; [
Measurement of Lowpass Filter Freq Response $ cd feed_fwd_2;$ T5 ^& [+ R. a2 N, O8 D
" n+ G" L9 }& J2 ~6 YPLLs
' D, z! ~' s% O7 i VCO with phase noise $ cd 9 H9 m1 A8 t! l- `
Pll with freq domain instruments $ cd \ams\pll; ' X) V6 K* t1 M& Y% y* g' m: B% x, E
Pll fractional with analog compensation $ cd \ams\pll; 3 j% @$ c1 Z6 y: m$ m, X
Pll fractional with digital compensation $ cd \ams\pll;
: ?/ U l/ o" f0 o Pll optimization (Nonlinear Control Design) $ cd \ams\pll; , v8 L7 ~. \+ a/ {! K! {6 B a
Carrier and Symbol Timing Recovery (NCO->ADC) $ cd \ams\pll; carrier_timing; / K% I9 ]; k9 H) v3 O$ ^; I
Carrier and Symbol Timing Recovery (Fractional Delay) $ cd \ams\pll; timing_recovery_1; |
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