Design of High-Voltage-Tolerant ESD Protection

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Design of High-Voltage-Tolerant ESD Protection
/ k' d8 u: E" N4 x- HCircuit in Low-Voltage CMOS Processes

' V- M- P- f! A% K6 `  K1 nMing-Dou Ker, Fellow, IEEE, and Chang-Tzu Wang, Student Member, IEEE

% x6 T1 ^$ g0 t, B. O5 LAbstract -- --
     Two new electrostatic discharge (ESD) protection design by using only 1 × VDD low-voltage devices for mixedvoltage I/O buffer with 3 × VDD input tolerance are proposed.
Two different special high-voltage-tolerant ESD detection circuits are designed with substrate-triggered technique to improve ESD protection efficiency of ESD clamp device. These two ESD detection circuits with different design concepts both have effective driving capability to trigger the ESD clamp device on. These ESD
protection designs have been successfully verified in two different 0.13-μm 1.2-V CMOS processes to provide excellent on-chip ESD protection for 1.2-V/3.3-V mixed-voltage I/O buffers. Index Terms—Electrostatic discharge (ESD), low-voltage CMOS, mixed-voltage I/O, substrate-triggered technique.

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