想請教各位先進要如何設計一個倒數器

wesley0905 · 發表於 2007-11-29 13:26:19

各位先進跟板大好

小弟現在再寫一個倒數器
是用Verilog來寫
現在只差led的部分倒數的部分我已經寫好了
倒數器我是用一個計數器來寫 , 但是計數器是16進制
而我的led是要10進制的來顯示 ,
所以想請問各位先進跟板大要著麼去寫
讓16進制轉10進制led
thanks!!

wesley0905 · 發表於 2007-11-29 13:32:01

`timescale 1ns/1ns
module reciprocal_counter_96_11_29 (
                     clk,
                     reset,
                     min_1,
                     min_5,
                     min_10,
                     start,
                     reset_ext,
                     ok
//外部腳位定義-------------------------------------
input clk , reset ;          //系統 clk reset
input min_1 , min_5 , min_10;  //設定每按一次1加1按5加一次5按10加一次10
input start;                //開始倒數鍵
input reset_ext;             //強制歸零並停止倒數
input ok;             //用來關掉alarm鬧鈴
//宣告內部暫存器---------------------------------------
wire clk , reset , min_1 , min_5 , min_10 , start , reset_ext; //宣告clk , reset , min_1 , min_5
                                 // min_10 , start , reset_ext為連接線
reg [9:0]counter;                         //宣告counter為暫存器
reg min_1_b;                            //宣告min_1_b為暫存器
reg min_1_bb;                            //宣告min_1_bb為暫存器
wire pulse_1;                            //宣告pulse_1為連接線
reg min_5_b;                            //宣告min_5_b為暫存器
reg min_5_bb;                            //宣告min_5_bb為暫存器
wire pulse_5;                            //宣告pulse_5為連接線
reg min_10_b;                            //宣告min_10_bb為暫存器
reg min_10_bb;                            //宣告min_10_bb為暫存器
wire pulse_10;                            //宣告pulse_10為連接線
reg alarm;                            //宣告alarm為暫存器
reg ok_b;                            //關掉alarm鬧鈴的暫存器
reg ok_bb;                            //關掉alarm鬧鈴的暫存器
wire pulse_ok;                            //關掉alarm鬧鈴的訊號
reg reset_ext_b;                         //關掉外部歸零的暫存器
reg reset_ext_bb;                         //關掉外部歸零的暫存器
wire pulse_reset_ext;                         //關掉外部歸零的訊號
reg count_d ;                            //宣告啟動alarm用
reg count_dd ;                            //宣告啟動alarm用
wire pulse_d ;                            //宣告啟動alarm用
reg [7:0]led  ;

assign pulse_1 = min_1_b & ~min_1_bb;
assign pulse_5 = min_5_b & ~min_5_bb;
assign pulse_10 = min_10_b & ~min_10_bb;
assign pulse_d = count_d & ~count_dd ;
assign pulse_ok = ok_b & ~ok_bb;
assign pulse_reset_ext = reset_ext_b & ~reset_ext_bb;
//-----------------------------------------------------
//計數跟倒數
//-----------------------------------------------------
always @ (posedge clk or negedge reset)
begin
if(~reset)
   counter <= 0;          //把counter 設初始值為零
else if(pulse_1)          //
   counter <= counter + 1;       //
else if(pulse_5)          //設定counter按1 and 5 and 10的累加
   counter <= counter + 5;       //
else if(pulse_10)          //
   counter <= counter + 10;       //
else if(counter >0 & start)          //設定counter開始倒數
   counter <= counter - 1 ;       //
else if(pulse_reset_ext)          //設定reset_ext強制關掉所有目前正在執行的動作
   counter <= 0 ;
end

//------------------------------------------------------
//led_counter
//------------------------------------------------------

//-------------------------------------------------------
//alarm鬧鈴
//------------------------------------------------------
always @ (posedge clk or negedge reset )
begin
if(~reset)
         alarm <= 0 ;                      //設定alarm鬧鈴初始值為零
      else if(pulse_ok)                   //設定當pulse_ok為1時成真,alarm為0關掉鬧鈴
         alarm <=  0 ;                         //
      else if(pulse_d)             //設定在counter倒數數到零零零時鬧鈴為1聲響起
         alarm <=  1 ;
end
//-----------------------------------------------------
//count_d
//----------------------------------------------------
always @ (posedge clk or negedge reset)
begin
if(~reset)
   count_d <= 0;
else if(start & counter == 2)
   count_d <= 1 ;
// else if(pulse_reset_ext)
   else
   count_d <= 0;



end
//--------------------------------------------------------------
//count_dd
//--------------------------------------------------------------
always @ (posedge clk or negedge reset)
begin
if(~reset)
      count_dd <= 0 ;
else if (start & counter == 1)
   count_dd <= count_d ;
// else if(pulse_reset_ext)
else
   count_dd <= 0;

end

續1

wesley0905 · 發表於 2007-11-29 13:33:19

//-----------------------------------------------------
//min_1_b
//-----------------------------------------------------
always @ (posedge clk or negedge reset)
begin
if(~reset)
   min_1_b <= 0;
else
   min_1_b <= min_1;
end
//-------------------------------------------------
//min_1_bb
//-------------------------------------------------
always @ (posedge clk or negedge reset)
begin
if(~reset)
   min_1_bb <= 0;
else
   min_1_bb <= min_1_b;
end

//--------------------------------------------------
//min_5_b
//-------------------------------------------------
always @ (posedge clk or negedge reset)
begin
if(~reset)
   min_5_b <= 0;
else
   min_5_b <= min_5;
end
//----------------------------------------------------------
//min_5_bb
//----------------------------------------------------------
always @ (posedge clk or negedge reset)
begin
if(~reset)
   min_5_bb <= 0;
else
   min_5_bb <= min_5_b;
end
//--------------------------------------------------------------
//min_10_b
//--------------------------------------------------------------
always @ (posedge clk or negedge reset)
begin
if(~reset)
   min_10_b <= 0;
else
   min_10_b <= min_10;
end
//---------------------------------------------------------------
//min_10_bb
//---------------------------------------------------------------
always @ (posedge clk or negedge reset)
begin
if(~reset)
   min_10_bb <= 0;
else
   min_10_bb <= min_10_b;
end
//--------------------------------------------------------------
//ok_b
//--------------------------------------------------------------
always @ (posedge clk or negedge reset)
begin
if(~reset)
   ok_b <=0;
else if(ok)
   ok_b <= ok  ;
   else
   ok_b <= 0;


end
//--------------------------------------------------------------
//ok_bb
//--------------------------------------------------------------
always @ (posedge clk or negedge reset)
begin
if(~reset)
   ok_bb <= 0;
else if(ok_b)
   ok_bb <= ok_b;
else
         ok_bb <= 0 ;

end
//----------------------------------------------------------------
//reset_ext_b
//---------------------------------------------------------------
always @ (posedge clk or negedge reset)
begin
if(~reset)
   reset_ext_b <=0;
else if(reset_ext)
   reset_ext_b <= reset_ext;
else
   reset_ext_b <= 0 ;
end
//-----------------------------------------------------------------
//reset_ext_bb
//-----------------------------------------------------------------
always @ (posedge clk or negedge reset)
begin
if(~reset)
   reset_ext_bb <= 0;
else if(reset_ext)
   reset_ext_bb <= reset_ext_b;
else
   reset_ext_bb <= 0 ;
end
endmodule
續2

wesley0905 · 發表於 2007-11-29 13:35:04

min_5,
   min_10,
   start,
   reset_ext,
   ok
            );
output clk , reset ; //設定送給系統clk , reset訊號
output min_1 , min_5 , min_10 ; //設定送給按1 and 5 and 10累加訊號
output start ; //設定送給start 開始倒數的訊號
output reset_ext ; //設定送給reset_ext強制關掉倒數計時並強制歸零的訊號
output ok; //設定送給reset_ext強制關掉倒數計時並強制歸零的訊號
//-------------------------------------------

reg clk , reset , min_1 , min_5 , min_10 , start , reset_ext ,ok ;
always #(100) clk = ~clk ;

initial
begin
   #10
   clk = 0;
   reset = 0;
   min_1 = 0;
   min_5 = 0;
   min_10 = 0;
   start = 0;
   reset_ext = 0;
   ok = 0;
   #10
   reset = 1;
//---------------------------------------------------------------
//test start測試開始
//---------------------------------------------------------------
//---------------------------------------------------------------
//min_1_test
//---------------------------------------------------------------
repeat(10) @(posedge clk);          //repeat(重複)10次當clk發生在正緣時上面宣告一個完整的clk cycle要200s,
   min_1 = 1 ;
   min_5 = 0 ;
   min_10 = 0 ;

repeat(10) @(posedge clk);          //repeat(重複)10次當clk發生在正緣時上面宣告一個完整的clk cycle要200s,
   min_1 = 0 ;
   min_5 = 0 ;
   min_10 = 0 ;
   start = 0 ;
//--------------------------------------------------------------
//min_5_test
//--------------------------------------------------------------
repeat(10) @(posedge clk);          //repeat(重複)10次當clk發生在正緣時上面宣告一個完整的clk cycle要200s,
   min_1 = 0 ;
   min_5 = 1 ;
   min_10 = 0 ;

repeat(10) @(posedge clk);          //repeat(重複)10次當clk發生在正緣時上面宣告一個完整的clk cycle要200s,
   min_1 = 0 ;
   min_5 = 0 ;
   min_10 = 0 ;

//---------------------------------------------------------------
//min_10_test
//---------------------------------------------------------------
repeat(10) @(posedge clk);          //repeat(重複)10次當clk發生在正緣時上面宣告一個完整的clk cycle要200s,
   min_1 = 0 ;
   min_5 = 0 ;
   min_10 = 1 ;

repeat(10) @(posedge clk);          //repeat(重複)10次當clk發生在正緣時上面宣告一個完整的clk cycle要200s,
   min_1 = 0 ;
   min_5 = 0 ;
   min_10 = 0 ;
   reset_ext = 0;

repeat(10)
begin

//------------------------------------------------------------------
//min_10_test
//------------------------------------------------------------------
repeat(10) @(posedge clk);          //repeat(重複)10次當clk發生在正緣時上面宣告一個完整的clk cycle要200s,
   min_1 = 0 ;
   min_5 = 0 ;
   min_10 = 1 ;

repeat(10) @(posedge clk);          //repeat(重複)10次當clk發生在正緣時上面宣告一個完整的clk cycle要200s,
   min_1 = 0 ;
   min_5 = 0 ;
   min_10 = 0 ;

end
   start = 1 ;                   //設定start為high開始倒數
   #100000
   start = 0 ;          //設定clk 跑100000us 之後主要是讓他倒數數到零
   ok = 1 ;          //設定ok為high把alarm關掉
   #10;          //過10us clk
   ok = 0;
   #10;
   reset_ext = 1 ;          //設定reset_ext為high時關掉所有計數跟倒數
   #10;
   reset_ext = 0 ;
   #10;          //ok設為low
   rerun ;
//    reset_ext = 1 ;          //設定reset_ext為high時關掉所有計數跟倒數
//    #10;
//    reset_ext = 0 ;
   #10;
   rerun ;
//    reset_ext = 1 ;          //設定reset_ext為high時關掉所有計數跟倒數
//    #10;
//    reset_ext = 0 ;
//    #100000
//    ok = 1 ;
end
續3 testbench

wesley0905 · 發表於 2007-11-29 13:35:56

//---------------------------------------------------------------
//test start測試開始
//---------------------------------------------------------------
task rerun;
begin
//---------------------------------------------------------------
//min_1_test
//---------------------------------------------------------------
repeat(10) @(posedge clk);          //repeat(重複)10次當clk發生在正緣時上面宣告一個完整的clk cycle要200s,
   min_1 = 1 ;
   min_5 = 0 ;
   min_10 = 0 ;

repeat(10) @(posedge clk);          //repeat(重複)10次當clk發生在正緣時上面宣告一個完整的clk cycle要200s,
   min_1 = 0 ;
   min_5 = 0 ;
   min_10 = 0 ;
   start = 0 ;
//--------------------------------------------------------------
//min_5_test
//--------------------------------------------------------------
repeat(10) @(posedge clk);          //repeat(重複)10次當clk發生在正緣時上面宣告一個完整的clk cycle要200s,
   min_1 = 0 ;
   min_5 = 1 ;
   min_10 = 0 ;

repeat(10) @(posedge clk);          //repeat(重複)10次當clk發生在正緣時上面宣告一個完整的clk cycle要200s,
   min_1 = 0 ;
   min_5 = 0 ;
   min_10 = 0 ;

//---------------------------------------------------------------
//min_10_test
//---------------------------------------------------------------
repeat(10) @(posedge clk);          //repeat(重複)10次當clk發生在正緣時上面宣告一個完整的clk cycle要200s,
   min_1 = 0 ;
   min_5 = 0 ;
   min_10 = 1 ;

repeat(10) @(posedge clk);          //repeat(重複)10次當clk發生在正緣時上面宣告一個完整的clk cycle要200s,
   min_1 = 0 ;
   min_5 = 0 ;
   min_10 = 0 ;
   reset_ext = 1;
repeat(10)

begin
//------------------------------------------------------------------
//min_10_test
//------------------------------------------------------------------
repeat(10) @(posedge clk);          //repeat(重複)10次當clk發生在正緣時上面宣告一個完整的clk cycle要200s,
   min_1 = 0 ;
   min_5 = 0 ;
   min_10 = 1 ;

repeat(10) @(posedge clk);          //repeat(重複)10次當clk發生在正緣時上面宣告一個完整的clk cycle要200s,
   min_1 = 0 ;
   min_5 = 0 ;
   min_10 = 0 ;

end
   start = 1 ;                   //設定start為high開始倒數
   #100000
   start =0 ;          //設定clk 跑100000us 之後主要是讓他倒數數到零
   ok = 1 ;          //設定ok為high把alarm關掉
   #10;          //過10us clk
   ok = 0 ;
   #10;          //ok設為low
   reset_ext = 1 ;
   #10;
   reset_ext = 0 ;

//    start = 1 ;
//    #100000                   //設定clk 跑100000us 之後主要是讓他倒數數到零
//    ok = 1 ;          //設定ok為high把alarm關掉
//          //過10us clk
//    reset_ext = 1;
end
endtask
endmodule
續4 testbench

wesley0905 · 發表於 2007-11-30 12:06:29

恩板大說的對
昨天同事跟我說 , 要我一開始就用10進位的倒數器來做就好這樣最快
就不用在那邊想說要再轉一次 ,
那可否再請教一下板大
要設計一個10進位倒數
以我之前po的程式上要從那著手修改呢
thanks

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感謝板大

[問題求助] 想請教各位先進要如何設計一個倒數器

這是小弟寫的倒數器續2

這是小弟寫的倒數器續3 testbench

這是小弟寫的倒數器續4 testbench