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Please select the following issues that you believe EDA Tool Vendors should invest in based on your experience and design needs. :o ) l1 ~1 b" y) I* B: E
& a6 f* c: T1 \; S0 V6 z/ p) rAdd your comments to further explain how these issues are impacting your design process. And let's discuss these before 2008.
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1.Time and schedule0 e! K! v3 R, Z( Z: r
2.Parallel designs e.g. layout and design engineering working at the same time R9 G6 T& `! h1 U
3.DRC/LVS/ANT verification/ X W! i! _5 t9 H
4.DFT9 w, Q6 U! X& u' B
5.Working in a multi user environment
- G& Y$ m8 s6 ^ Q2 K/ ]6.Incorporating latest process node specifics (e.g. .65, .45 CMOS)
' R1 y! p1 E5 Y+ u- [$ `7.More than Moore technologies, such as high voltage design, high frequency design, high current design, high temperature design, multiple
$ M' @2 l; V* M$ [' I6 c technology support in a single design, Mems
! t+ V& v3 W9 t8 E8.Incorporating RF blocks into standard designs (RF SoC Design)
" n" K9 x! Z1 x9.Dealing with low-power design constraints in an analog world! X1 S1 g% f' _ u, H" z
10.Entering, tracking and verifying design intent between electrical and physical design; H( C. G( v0 i3 e
11.Assessing parasitic sensitivities prior to full layout
9 E2 ]7 G8 C$ G# l3 F* Y12.Optimizing circuit construction at 65nm and below
" r. ?8 V6 F5 L. }6 L. f$ Q9 u13.Techniques for design centering to achieve optimum performance / yield
7 g. n# i, _: b" M, |6 M14.Designing up to to six-sigma yield margins
: P3 F- b; B4 | ^! j+ Y1 m15.Other, please specify: |
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