Month$ `) d3 s7 @5 y
| Topic
# S4 ~; ~+ K2 M. a: Q& s2 M |
January) j# }( b% s2 a0 D. |
| • Parasitics & Parasitic Extraction0 N( W3 w4 X4 b( g7 W
|
February& ?0 |# U5 |9 Q, q
| • Verification Methodologies & Tools1 r/ C2 m6 S7 c* m7 U
• CAE/CAD Tools for FPGAs. c; M$ U: |) }( p
|
March
( l) U. _# J; C& m% j% n V | • Configurable & Reconfigurable Processors
2 G1 J& b& q- V9 P) S: @ |
April
1 u3 T& m _4 Z) Z" j | • Hardware/Software Co-Design
3 W% t+ N9 M- e• On-chip Interconnect, Network on chip (NoC)
/ f0 d: I0 A, ]4 q( v, K |
May
6 z: Z1 }; `- H' ~* W$ v$ F, F4 \ | • Electronic System Level Design (ESL)
7 F) m% Z' Z0 t0 h9 }5 h, e. e |
June
* b# t" e" D6 Y8 A# M | • Timing Analysis, Closure, & Sign-off1 u7 b3 t, k9 }; n
• Low-power Design Methodologies & Tools
/ \0 l6 [4 h4 Y) p" w D/ r |
July
4 M% A6 y/ m/ a& Y4 d; p | • FPGAs in DSP Applications9 \+ E v" H+ t
|
August# ?" J9 B2 D8 W$ i
| • Formal Verification Methodologies & Tools
" Y4 c7 ?6 b8 f) h+ k |
September& q3 i7 G+ ^" a$ J- f* p- ?
| • Structured ASICs & FPGA-to-ASIC Conversion" G9 G, w3 Y; M0 O/ J6 {
• Design-for Manufacturing/Yield (DFM & DFY) 6 \& u8 T' H$ f) W3 d b9 |
|
October
9 A+ L, t5 }% H D, z3 b6 u | • ATPG, BIST & DFT P2 N" |0 n4 k `; E4 d
|
November
0 ^' j& Y4 s: [* D, x7 r. e! U | • Physical Design (Partitioning, Floorplanning & Placement, Routing, Optimization)4 |1 z) S- P1 w3 ~3 D) i3 T
• Device/Circuit Modeling & Simulation: X5 L8 p! m9 m" ~$ e, ^
|
December( j' v3 L4 ~/ |3 x
| • Analog & Mixed-Signal Design9 m" z8 I) y# c3 v
|