|
IPextreme, Inc. / White Paper0 @5 R! P9 F5 e% b8 W; w
$ P" o4 K9 f/ E9 e! H3 vWhite Paper Content:7 a" s6 O! F% y P0 |% J, O' {
X. a+ h/ e1 m! c
The speed and density of today's multi-core SoCs have outgrown traditional debugging methodologies. To debug a system in its target environment, where problems often only occur, a debugger needs access to an enormous amount of trace data from various processors, buses, and signals within the SoC. Getting this data off-chip to the debugger in real time requires on the order of 100 Gbits/sec of bandwidth at the chip I/O, which is not practical using either dedicated debug pins or shared debug/functional pins. The problem is further compounded by the need to analyze all of that data.3 Q- k* M g8 [; F6 B0 \6 H
5 r' ]4 u5 K8 ~# j+ ?. w8 s
Infineon has successfully developed and deployed a technology known as the Multi-Core Debug Solution(MCDS)to address that problem. Using advanced on-chip trace techniques that include on-chip trigger generation, trace data compression, and trace storage, MCDS provides only the relevant trace data to the debug tool. Without adding pins to the chip, MCDS enables real-time, in-system debug and performance optimization.
, x5 B: t, U7 m$ v/ W0 j$ e4 Y4 _
|
評分
-
查看全部評分
|