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LOAD SDC FILE時
; l& H5 A; r* g6 pAstro 訊息7 p% R+ W4 t# K# N: ~$ X
---------------------------------------------------------------------------
9 g, [: F* `# u0 B- G! fInfo: starting Tcl processing
- n: s& j+ ?. }8 q4 dInfo: building design object name tables
0 m' R/ o4 i9 _0 M" o1 R( L5 l; KWarning: No pins matched 'TOP/test/mul/A[26]' (SEL-004)
! o2 {- J K5 s# g7 {+ i5 JWarning: No pins matched 'TOP/test/mul/A[25]' (SEL-004)2 `/ Q! u% @5 R) ]; r& u
. D: Y/ f, f1 H e8 d
----------------------------------------------------------------------------7 J7 @. s" g# R8 i v
SDC FILE
; l5 @4 ~! z2 V8 b& a
( H, U7 I N' W' fset_multicycle_path 9 -through [list [get_pins \
6 G; r7 F9 ]4 A{TOP/test/mul/A[26]}] [get_pins \
+ E7 y0 A8 ~4 ^{TOP/test/mul/A[25]}] [get_pins \
& N. F. V' E- K t- o) n
! L+ |9 {! p4 S) R3 M) q) A/ h$ o+ ~( n
% |$ t7 f. R/ U9 R-----------------------------------------------------------------------------2 ^- \- [3 }) ~2 X/ B& b
Verilog File
2 o( P, y' S8 \5 i" y
' T* X+ U, p% b7 T4 `2 ?0 | uniquify_mul_0 mul ( .A(icwAeYfSum[26:0]), .B(
- ~6 q1 A8 e+ l; c* c2 N( V icwAeYfNum[18:0]), .C(ae_avg) ); |
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