When PCB layout area is not enough, we often use 4mil GND trace to shielding RF clock trace with 4mil spacing.9 o# E! H% `' @5 P
Is this way enough to avoid RF clock signal to couple other signal trace near the 4mil trace? 3 ]9 R% }; t8 |Thanks
u r proposed to refer to 3W rule. 7 {6 c i [+ N
when clock trace is 5 mils, u will need 10 mils spacing. ! G% r9 g* m9 ^& ?$ Q. V) Kof course GND trace will help, but PTH through holes with proper interval will do it better. 1 u7 e" L+ l7 @! Y7 a4 @3 s: l1 ~% n! v$ e5 l; t, {) m1 ~
google it for detailed information, please!