ise 9.2出來哦

tommywgt

ISE 9.2i continues to deliver the performance leadership.
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3 J; Z+ Q# w0 k4 RTiming closure without floorplanning
* ]  G: E, Z7 H8 ^2 zImproved pre-routing delay estimation allowing upstream tools to optimize true critical path
/ r3 M# T4 G# k) h# vLeveraging of the Virtex™-5 Diagonal Interconnect to optimize for delay
/ a  X; x: s9 \$ eSupport for 6LUT for improved performance, power, and utilization
. B$ \  \$ j7 I  @9 E/ B" ~Fewer LUTs → Less routing and fewer logic levels → Higher performance and Lower power
Physical Synthesis Optimizations
ISE 9.2i design tools build on capabilities of ISE Fmax Technology, especially designed to deliver unparalleled performance and timing closure results for high density, high performance Virtex-5 based designs. The ISE 9.2i integrated timing closure flow incorporates enhanced physical synthesis optimizations that provide optimal clock placement, better packing, and timing-driven mapping for higher quality of results.

8 c8 f( O5 J! @) E) NOptimized routing algorithms provide the most efficient utilization of the diagonally symmetric interconnect of the 65nm ExpressFabric™ to minimize delay and fully leverage the high performance features of the Virtex-5 Platform. ISE 9.2i routing algorithms also support pin swapping based on timing requirements to further maximize design performance
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Underlying the entire ISE 9.2i infrastructure is an expanded timing closure environment – a virtual “Timing Closure Cockpit” – that enables seamless cross-probing between constraint entry, timing analysis, floorplanning and report views so designers can more easily analyze timing problems.

Productivity
) B- J  L: j6 C% E5 L& lIntroducing new SmartCompile Technology
+ v" \9 f: ^0 ?2 IImprovements in the mapping, placement, and routing algorithms allow users to realize an average of 2.5X faster compile times, for tough designs. This allows users to get more implementations, or turns, of their designs enabling faster time-to-market and less frustration.
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7 A  a- g* s; h7 W' FFPGA designers can realize an additional 2.5X faster runtimes, on average, with SmartCompile Technology in ISE 9.2i with some designs achieving up to 6X faster runtimes for incremental changes.

) z4 G& m" H, U. E2 I+ aSmartCompile is comprised of three new features; SmartGuide, Partitions, and SmartPreview.
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+ F2 d9 A8 k* ]Partitions deliver guaranteed preservation of existing implementation. Users can define Partitions, or hierarchical blocks, within their design. They can then specify that the synthesis, placement, and/or routing of these partitions are to be preserved during re-implementation.
SmartGuide minimizes implementation differences between two versions of the same design. SmartGuide is available from the ISE Project Navigator and does not require substantial changes to an existing design flow. Faster runtimes will be realized and timing preserved for small design changes that are not on a critical path.
8 g% \9 i5 Y+ _  z& |' @& ASmartPreview allows users to pause and resume implementation. This allows the user to save intermediate results, view state of design (paths that fail timing, routing status), generate bitstreams, and perform timing analysis. This reduces the impact of long implementation cycles by providing insight into the implementation process.
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ISE 9.2i includes other new features to help designers quickly achieve timing closure including:
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Tcl Command Window: The Tcl window allows users to easily navigate between the ISE graphical environment and the command line.
" K* h$ U+ @1 V0 g3 N% g  @: C* kSource Code Control Capabilities: Allows users to quickly and easily identify the files associated with a known version of their design. They can then export the source files and scripts needed to regenerate the project with the same sources and settings.
Integrated Timing Closure Environment: The Integrated Timing Closure Environment has provides a virtual timing-closure cockpit. This integration of PACE, the timing analyzer, constraints editor, and the floorplanner view allows cross probing between those views and the ISE Design Summary. This allows users to explore their design and address problems from multiple angles. The Integrated Timing Closure Environment is available for Virtex-5, Virtex-4, and Spartan™-3A devices.
Power
Lower Dynamic Power by an Average 10%
- x: z# \( Y3 j8 x3 h2 HAdvanced synthesis and implementation algorithms deliver 10% lower dynamic power
$ l$ ?6 e4 z' G) TFree, downloadable XPower Estimator spreadsheets for the leading Xilinx FPGAs lets customers quickly and easily estimate their project's power consumption with device-specific spreadsheet tools.
4 j, r) A7 |. K3 ]1 o+ LXPower Analyzer included with all configuration of ISE performs detailed design-based power consumption analysis, including importing simulation files for detailed design accuracy.
Find answers to your power-related questions at Xilinx Power Central, www.xilinx.com/power

tommywgt

講了這麼多, 我覺得

1) ise9.2 把ise9.1的功能加上3個service pack合在一起了
2) smart guide 跟 smart complier在9.1就有了, 我個人覺得很好用, 沒用過的人可以試試
3) 在時序收歛上, 我一直沒遇到這個問題, 有人有遇到解決不了的嗎?
$ g- C7 ^( o3 i2 o) H4) 我建議用dual core的電腦去compiler會快很多
5) 在時序有問題時, 不妨試試floor planer跟FPGA editor這二套都內建在ISE內

- w6 g% F7 ]7 l% p) ?+ a* h$ T) M3 L基本上我覺得tool的問題通常不會太大, 真的有問題的話我都習慣從RTL著手
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另外, ISE9.2的service pack出哦, 要250MB...XD
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4 B6 [( ^* g1 ^7 o$ EISE有內建MIG (有人不知道MIG的嗎?)
& w" t" q9 Y- w0 y+ s在過去 ise9.1要安裝 service pack2才能執行MPMC2; 要裝service pack1才能支援3ADSP
5 `; D  K3 ]8 A# Z現在都ok了

tommywgt

忘了補充...
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1 W8 z' C- L6 ~% p. M# d( fmodelsim OEM版也出了, ChipScopePro只出9.2 emulation 版, 其他的還要等一下下

jason_lin

補充一下,
8 R/ M2 l; P7 {. W0 H( h" ~. A! dISE9.2支援Windows Vista.
ISE9.1不支援Windows Vista,支援XP 64bit,32bit.
其他只支援XP 32bit.