Month
: j& P& {2 o5 ]( [( u, T+ d | Topic
- m+ w0 E& M+ q. p4 N |
January7 ]- U$ g# y0 G+ G/ m* m
| • Parasitics & Parasitic Extraction- j- o' }* }% U1 }
|
February+ k) b, |+ \- f5 p
| • Verification Methodologies & Tools
5 d$ O7 c3 `/ E$ z' B" `+ l) w• CAE/CAD Tools for FPGAs7 N1 S: a4 e( T
|
March2 k" o/ p! W8 m- A
| • Configurable & Reconfigurable Processors: v/ D- L1 s) Z2 ?6 E% Z: R: C4 r0 u
|
April4 {7 j+ l4 @8 _; \! M. r
| • Hardware/Software Co-Design
0 e" w) {; S; [+ o6 A4 N• On-chip Interconnect, Network on chip (NoC) + \- @2 b, ~* k" h0 F
|
May
* r: q, R# p# ^$ Z! K | • Electronic System Level Design (ESL)* B/ t# [% z: p- w: S3 }+ R
|
June# Z) ? }8 L: S. `1 L5 u0 S
| • Timing Analysis, Closure, & Sign-off
0 N! i2 b" Y3 a2 N9 v8 n• Low-power Design Methodologies & Tools
% `' X* l, A- [9 \2 Y" J |
July
0 o' ], h1 G9 a8 s% B( R( P | • FPGAs in DSP Applications
( Y' S$ Z5 R5 ~5 }( k$ {3 C+ e |
August
7 _- I/ [' S' W# ^( o | • Formal Verification Methodologies & Tools. J" P0 }0 S) }+ E R# G: l
|
September$ G+ \5 r5 ]' g( r- ]/ I1 d
| • Structured ASICs & FPGA-to-ASIC Conversion5 E7 P. S! w7 ?0 D5 n& T
• Design-for Manufacturing/Yield (DFM & DFY) ) W5 f& e7 e1 \; ~
|
October
, D+ D+ W9 o4 c3 X. `+ S$ F | • ATPG, BIST & DFT
$ W; b$ ]6 e3 m; h% x |
November, D. z+ Z: i- C
| • Physical Design (Partitioning, Floorplanning & Placement, Routing, Optimization)
$ I( X, _8 }( I& v6 Y2 ]• Device/Circuit Modeling & Simulation! `2 }5 ?! l" h+ K0 ?. }, v
|
December5 m7 \: \4 S/ v. S' ]5 \, F
| • Analog & Mixed-Signal Design
6 s/ \8 Z" Q5 N3 {. I( X |