求助 ! 誰會以verilog寫一個 "時鐘" 的程式

austinchang2002 · 發表於 2007-6-22 15:49:19

Dear all ,

請問有誰曾經以verilog寫過一個 " 時鐘 "的程式 ,

還有 , 是否可提供相關的程式做參考 , 或給予建議 .

感激不盡 .......

Austin.Chang

masonchung · 發表於 2007-6-22 19:29:14

是時鐘程式,還是時鐘電路?

lilianChen · 發表於 2007-6-23 21:49:26

來個e-mail 吧~~~我有寫個只有秒跟分,外接七段顯示器的example code~~且在xilinx的 tool ise 9.0 以及 xc95108 的 start kit 上驗證過的code

eject · 發表於 2007-7-8 09:42:29

當年用 TTL 大概是 15 顆左右吧
後來才知道耗電才是時鐘 DESIGN 的重點

wesley0905 · 發表於 2007-11-30 12:10:38

我的時鐘是設計秒:S 分:M 時:H 不知是不是你要的
`timescale 1ns/1ps

module clock (
      clk,
      reset,
      cou_s,
      cou_m,
      cou_h,
      switch,
            set,
            m_set,
            h_set
      );

input clk;
input reset;
input switch;
input set;
input m_set;
input h_set;
output [5:0]cou_s;
output [5:0]cou_m;
output [3:0]cou_h;

wire clk ;
wire reset;
wire switch;
wire set;
wire m_set;
wire h_set;
reg [5:0]cou_s;
reg [5:0]cou_m;
reg [3:0]cou_h;
reg alarm;
reg [5:0]acou_s;
reg [5:0]acou_m;
reg [3:0]acou_h;
reg [9:0]count_a;

//cou_s_時鐘秒的計數器------------------------------------------------
always @(posedge clk or negedge reset)
begin
if(~reset)
   cou_s <= 0;
else if (cou_s == 6'h3c)
   cou_s <= 0;
else
   cou_s <= cou_s + 1;
end

//cou_m_時鐘分的計數器-------------------------------------------
always @(posedge clk or negedge reset)
begin
if(~reset)
   cou_m <= 0;
else if(cou_s == 6'h3c)
         cou_m <= cou_m + 1;
else if(cou_m == 6'h3c)
   cou_m <= 0;
end

//cou_h_時鐘小時的計數器---------------------------------------------
always @(posedge clk or negedge reset)
begin
if(~reset)
   cou_h <= 0;
else if(cou_m == 6'h3c)
   cou_h <= cou_h + 1;
else if(cou_h == 4'hc)
   cou_h <= 1;
end

//acou_h_鬧鈴小時的計數器------------------------------------------
always @(posedge clk or negedge reset)
begin
if(~reset)
   acou_h <= 0;
else if(acou_h == 4'h4)
   acou_h <= acou_h ;
else if(acou_m == 6'h3c)
   acou_h <= acou_h + 1;
else if(acou_h == 4'hc)
   acou_h <= 1;
end

//acou_m_鬧鈴分時的計數器-----------------------------------------
always @(posedge clk or negedge reset)
begin
if(~reset)
   acou_m <= 0;
else if(acou_s == 6'h3c)
   acou_m <= acou_m + 1;
else if(acou_m == 6'ha)
      acou_m <= acou_m ;
else if(acou_m == 6'h3c)
   acou_m <= 0;
end

//acou_s_鬧鈴秒時的計數器-----------------------------------------
always @(posedge clk or negedge reset)
begin
if(~reset)
   acou_s <= 0;
else if(acou_s == 6'h3c)
   acou_s <= 0;
else
   acou_s <= acou_s + 1;
end

//alarm_鬧鐘------------------------------------------
always @(posedge clk or negedge reset)
begin
      if(~reset)
         alarm <= 0;
      else if(acou_h == 4'h4 & acou_m == 6'ha )
         alarm <= 1;
      else if(count_a == 10'h258)
         alarm <= 0;
//       else if(count_a == 9'h258
//          alarm <= 1;
//       else if(count_a == 9'h258
//          alarm <= 0;
//       else
//          alarm <= alarm ;
//       else if(acou_m == 6'h14)
//          alarm <= alarm ;



//       else if (switch)
//          alarm <= 0;
end

//count_a----------------------------------------
always @(posedge clk )
begin
if(~reset)
   count_a <= 0;
else if(alarm)
   count_a <= count_a + 1;
else if(count_a == 10'h258)
      count_a <= 0;
end

//switch_設定用來關掉鬧鈴-----------------------------
//always @(posedge clk or negedge reset)
//begin
// if(~reset)
//    switch <= 0 ;
// else if(
//
//enc

endmodule
續一

wesley0905 · 發表於 2007-11-30 12:12:56

這是testbench部分
`timescale 1ns/1ps
module clock_tester (
      clk,
      reset,
      switch,
      set,
      m_set,
      h_set
      );

output clk;
output reset;
output switch;
output set;
output m_set;
output h_set;

reg clk;
reg reset;
reg switch;
reg set;
reg m_set;
reg h_set;

always  #1 clk = ~clk ;  //設定clk每格一格變動一次
//初始值設定
initial
begin
   #5
   clk = 0;
   reset = 0;
   switch = 0;
   set = 0;
   m_set = 0;
   h_set = 0;
   #10
   reset =1;
//    switch=1;
//start test-------------
//one hour----------------
   #5
   set=1;
   h_set=1;
   m_set=0;
   #5
   set=0;
   h_set=0;
   m_set=0;
//two hours----------------
   #5
   set=0;
   h_set=1;
   m_set=0;
   #5
   set=0;
   h_set=0;
   m_set=0;
//three hours----------------
   #5
   set=0;
   h_set=1;
   m_set=0;
   #5
   set=0;
   h_set=0;
   m_set=0;
//four hours ----------------
   #5
   set=0;
   h_set=1;
   m_set=0;
   #5
   set=0;
   h_set=0;
   m_set=0;
//one minute----------------
   #5
   set=0;
   h_set=0;
   m_set=1;
   #5
   set=0;
   h_set=0;
   m_set=0;
//two minutes----------------
   #5
   set=0;
   h_set=0;
   m_set=1;
   #5
   set=0;
   h_set=0;
   m_set=0;
//three minutes----------------
   #5
   set=0;
   h_set=0;
   m_set=1;
   #5
   set=0;
   h_set=0;
   m_set=0;
//four minutes----------------
   #5
   set=0;
   h_set=0;
   m_set=1;
   #5
   set=0;
   h_set=0;
   m_set=0;
//five minutes----------------
   #5
   set=0;
   h_set=0;
   m_set=1;
   #5
   set=0;
   h_set=0;
   m_set=0;
//six minutes----------------
   #5
   set=0;
   h_set=0;
   m_set=1;
   #5
   set=0;
   h_set=0;
   m_set=0;
//seven minutes----------------
   #5
   set=0;
   h_set=0;
   m_set=1;
   #5
   set=0;
   h_set=0;
   m_set=0;
//eight minutes----------------
   #5
   set=0;
   h_set=0;
   m_set=1;
   #5
   set=0;
   h_set=0;
   m_set=0;
//nine minutes----------------
   #5
   set=0;
   h_set=0;
   m_set=1;
   #5
   set=0;
   h_set=0;
   m_set=0;
//ten minutes----------------
   #5
   set=1;
   h_set=0;
   m_set=1;
   #5
   set=0;
   h_set=0;
   m_set=0;

//    #1000
//    set =1;
//    h_set=1;
//    m_set=1;
//    #10
//    set=0;
//    h_set=0;
//    m_set=0;
//    #20000
//    set=1;
//    h_set=1;
//    m_set=1;
//    #10
//    set=0;
//    h_set=0;
//    m_set=0;

end
endmodule
續二

wesley0905 · 發表於 2007-11-30 12:14:19

這是test top
`timescale 1ns/1ps

module test_top();

wire clk ;
wire reset ;
wire cou_s ;
wire cou_m ;
wire cou_h;
wire set;


//clock module
clock U_clock (
         .set(set),
         .clk(clk),
         .reset(reset),
         .cou_s(cou_s),
         .cou_m(cou_m),
         .cou_h(cou_h),
         .switch(switch),
         .h_set(h_set),
         .m_set(m_set)
      );

//clock_tester module
clock_tester U_CLOCK_TESTER (
      .clk(clk),
      .reset(reset),
      .set(set),
      .switch(switch),
      .h_set(h_set),
      .m_set(m_set)
      );

initial

begin
$fsdbDumpfile("wave.fsdb");
$fsdbDumpvars();
end
endmodule
續三

greatsky · 發表於 2007-12-17 23:34:45

我想問一下,這時鐘的clk好像沒有delay
若直接跑的話,相對於實際的秒鐘來講會不會太快了?

kolong · 發表於 2007-12-21 17:14:58

應該會...
所以需要除頻.....
跟RTC的block一樣...

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[問題求助] 求助 ! 誰會以verilog寫一個 "時鐘" 的程式

這是我寫的時鐘程式~看看吧續一

這是我寫的時鐘程式~看看吧續二

這是我寫的時鐘程式~看看吧續三

[問題求助] 求助 ! 誰會以verilog寫一個 "時鐘" 的程式

這是我寫的時鐘程式~看看吧 續一

這是我寫的時鐘程式~看看吧 續二

這是我寫的時鐘程式~看看吧 續三

這是我寫的時鐘程式~看看吧續一

這是我寫的時鐘程式~看看吧續二

這是我寫的時鐘程式~看看吧續三